* [PATCH 1/4] riscv: sophgo: dts: add PCIe controllers for SG2042
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
@ 2025-10-20 3:33 ` Chen Wang
2025-10-20 3:34 ` [PATCH 2/4] riscv: sophgo: dts: enable PCIe for PioneerBox Chen Wang
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chen Wang @ 2025-10-20 3:33 UTC (permalink / raw)
To: u.kleine-koenig, aou, alex, unicorn_wang, conor+dt, rabenda.cn,
inochiama, krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
From: Chen Wang <unicorn_wang@outlook.com>
Add PCIe controller nodes in DTS for Sophgo SG2042.
Default they are disabled.
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index c5e49709b308..85d8b89cf9fc 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -240,6 +240,94 @@ clkgen: clock-controller@7030012000 {
#clock-cells = <1>;
};
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/4] riscv: sophgo: dts: enable PCIe for PioneerBox
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
2025-10-20 3:33 ` [PATCH 1/4] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
@ 2025-10-20 3:34 ` Chen Wang
2025-10-20 3:39 ` [PATCH 3/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Chen Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chen Wang @ 2025-10-20 3:34 UTC (permalink / raw)
To: u.kleine-koenig, aou, alex, unicorn_wang, conor+dt, rabenda.cn,
inochiama, krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index ef3a602172b1..c4d5f8d7d4ad 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -128,6 +128,18 @@ uart0-rx-pins {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
+&pcie_rc3 {
+ status = "okay";
+};
+
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
2025-10-20 3:33 ` [PATCH 1/4] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
2025-10-20 3:34 ` [PATCH 2/4] riscv: sophgo: dts: enable PCIe for PioneerBox Chen Wang
@ 2025-10-20 3:39 ` Chen Wang
2025-10-20 3:40 ` [PATCH 4/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Chen Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Chen Wang @ 2025-10-20 3:39 UTC (permalink / raw)
To: u.kleine-koenig, aou, alex, unicorn_wang, conor+dt, rabenda.cn,
inochiama, krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,
which uses SG2042 SoC.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
index 3320bc1dd2c6..a186d036cf36 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -164,6 +164,18 @@ phy0: phy@0 {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
` (2 preceding siblings ...)
2025-10-20 3:39 ` [PATCH 3/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Chen Wang
@ 2025-10-20 3:40 ` Chen Wang
2025-10-20 3:48 ` [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
2025-11-01 23:44 ` Inochi Amaoto
5 siblings, 0 replies; 10+ messages in thread
From: Chen Wang @ 2025-10-20 3:40 UTC (permalink / raw)
To: u.kleine-koenig, aou, alex, unicorn_wang, conor+dt, rabenda.cn,
inochiama, krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board,
which uses SG2042 SoC.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
index 46980e41b886..0cd0dc0f537c 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -152,6 +152,18 @@ phy0: phy@0 {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
` (3 preceding siblings ...)
2025-10-20 3:40 ` [PATCH 4/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Chen Wang
@ 2025-10-20 3:48 ` Chen Wang
2025-10-25 11:58 ` Han Gao
2025-11-01 23:44 ` Inochi Amaoto
5 siblings, 1 reply; 10+ messages in thread
From: Chen Wang @ 2025-10-20 3:48 UTC (permalink / raw)
To: Han Gao
Cc: Chen Wang, u.kleine-koenig, aou, alex, conor+dt, inochiama,
krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
hi, Han Gao,
Please help test this out on EVB, I don't have those boards and just
tested with my pinoeerbox.
Thanks,
Chen
On 10/20/2025 11:32 AM, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> This new patch set is a continuation of the previous patchset
> "[PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC" [1].
>
> The drivers and bindings have already been merged into the kernel
> mainline, and this patchset will focus on submitting the remaining
> DTS changes into the mainline.
>
> This patchset is based on v6.18-rc1 and the only changes since v3
> is a fix to address the comments from Manivannan Sadhasivam to make
> sure PCI address of the I/O port to start from 0.
>
> Link: https://lore.kernel.org/linux-riscv/cover.1757643388.git.unicorn_wang@outlook.com/ [1]
>
> Chen Wang (4):
> riscv: sophgo: dts: add PCIe controllers for SG2042
> riscv: sophgo: dts: enable PCIe for PioneerBox
> riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
> riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
>
> arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 +++
> arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 +++
> .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++++++++++
> 4 files changed, 124 insertions(+)
>
>
> base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC
2025-10-20 3:48 ` [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
@ 2025-10-25 11:58 ` Han Gao
2025-10-26 0:31 ` Chen Wang
0 siblings, 1 reply; 10+ messages in thread
From: Han Gao @ 2025-10-25 11:58 UTC (permalink / raw)
To: Chen Wang
Cc: Chen Wang, u.kleine-koenig, aou, alex, conor+dt, inochiama,
krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
On Mon, Oct 20, 2025 at 11:49 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>
> hi, Han Gao,
>
> Please help test this out on EVB, I don't have those boards and just
> tested with my pinoeerbox.
>
> Thanks,
>
> Chen
>
> On 10/20/2025 11:32 AM, Chen Wang wrote:
> > From: Chen Wang <unicorn_wang@outlook.com>
> >
> > This new patch set is a continuation of the previous patchset
> > "[PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC" [1].
> >
> > The drivers and bindings have already been merged into the kernel
> > mainline, and this patchset will focus on submitting the remaining
> > DTS changes into the mainline.
> >
> > This patchset is based on v6.18-rc1 and the only changes since v3
> > is a fix to address the comments from Manivannan Sadhasivam to make
> > sure PCI address of the I/O port to start from 0.
> >
> > Link: https://lore.kernel.org/linux-riscv/cover.1757643388.git.unicorn_wang@outlook.com/ [1]
> >
> > Chen Wang (4):
> > riscv: sophgo: dts: add PCIe controllers for SG2042
> > riscv: sophgo: dts: enable PCIe for PioneerBox
> > riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
> > riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
> >
> > arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 +++
> > arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 +++
> > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 +++
> > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++++++++++
> > 4 files changed, 124 insertions(+)
> >
> >
> > base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
EVB1.X/2.0 can be started normally.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC
2025-10-25 11:58 ` Han Gao
@ 2025-10-26 0:31 ` Chen Wang
2025-10-29 1:00 ` Inochi Amaoto
0 siblings, 1 reply; 10+ messages in thread
From: Chen Wang @ 2025-10-26 0:31 UTC (permalink / raw)
To: Han Gao, Inochi Amaoto
Cc: Chen Wang, u.kleine-koenig, aou, alex, conor+dt, inochiama,
krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li
On 10/25/2025 7:58 PM, Han Gao wrote:
[......]
>>> base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
> EVB1.X/2.0 can be started normally.
Thank you, Han.
Inochi, please add "Tested-by: Han Gao <rabenda.cn@gmail.com>" when you
pick this patchset for next.
Regards,
Chen
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC
2025-10-26 0:31 ` Chen Wang
@ 2025-10-29 1:00 ` Inochi Amaoto
0 siblings, 0 replies; 10+ messages in thread
From: Inochi Amaoto @ 2025-10-29 1:00 UTC (permalink / raw)
To: Chen Wang, Han Gao, Inochi Amaoto
Cc: Chen Wang, u.kleine-koenig, aou, alex, conor+dt, krzk+dt, mani,
liujingqi, palmer, pjw, robh, tglx, sycamoremoon376, devicetree,
linux-kernel, linux-riscv, sophgo, chao.wei, xiaoguang.xing,
fengchun.li
On Sun, Oct 26, 2025 at 08:31:49AM +0800, Chen Wang wrote:
>
> On 10/25/2025 7:58 PM, Han Gao wrote:
> [......]
> > > > base-commit: 3a8660878839faadb4f1a6dd72c3179c1df56787
> > EVB1.X/2.0 can be started normally.
>
> Thank you, Han.
>
> Inochi, please add "Tested-by: Han Gao <rabenda.cn@gmail.com>" when you pick
> this patchset for next.
>
Just add the tag is fine and no quote, I can collect the tag with b4.
Like this.
Tested-by: Han Gao <rabenda.cn@gmail.com>
Regards,
Inochi
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC
2025-10-20 3:32 [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
` (4 preceding siblings ...)
2025-10-20 3:48 ` [PATCH 0/4] Add PCIe support in DTS for Sophgo SG2042 SoC Chen Wang
@ 2025-11-01 23:44 ` Inochi Amaoto
5 siblings, 0 replies; 10+ messages in thread
From: Inochi Amaoto @ 2025-11-01 23:44 UTC (permalink / raw)
To: u.kleine-koenig, aou, alex, unicorn_wang, conor+dt, rabenda.cn,
krzk+dt, mani, liujingqi, palmer, pjw, robh, tglx,
sycamoremoon376, devicetree, linux-kernel, linux-riscv, sophgo,
chao.wei, xiaoguang.xing, fengchun.li, Chen Wang
Cc: Inochi Amaoto
On Mon, 20 Oct 2025 11:32:55 +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> This new patch set is a continuation of the previous patchset
> "[PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC" [1].
>
> The drivers and bindings have already been merged into the kernel
> mainline, and this patchset will focus on submitting the remaining
> DTS changes into the mainline.
>
> [...]
Applied to dt/riscv, thanks!
[1/4] riscv: sophgo: dts: add PCIe controllers for SG2042
https://github.com/sophgo/linux/commit/4e27aca4881ace1e9a812fc2c88b33dd84e29993
[2/4] riscv: sophgo: dts: enable PCIe for PioneerBox
https://github.com/sophgo/linux/commit/b85ad0d06a19de95d41f91162389a1bbb461a405
[3/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
https://github.com/sophgo/linux/commit/c6c215099e89b1eb71ed6592163ae5b530f4538e
[4/4] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
https://github.com/sophgo/linux/commit/579d6526aa43a155c8685a88ef8350a8c29afa47
Thanks,
Inochi
^ permalink raw reply [flat|nested] 10+ messages in thread