From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3640A2046BA for ; Tue, 13 May 2025 21:53:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173236; cv=none; b=RQ5PbjuEQ/6V3MiufvhNMqzGkTeO+R2twY8fudORoUrgQzPrPmKKtAkA4oR0l9TeQfof3eQgAUIz0PObGCV2o/ylvnMyj3LmSuIgV/K3sb7EGGeCzp/R+51Qp3KgBVYpVUJkT60GAdjCaEvelaGvFNlOsSUD5xPQvWEduhNOcKE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747173236; c=relaxed/simple; bh=EyJalHu7AkVtbvuCmvKRErn0E8ZxTM787Cwkb6tY49w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OgHHbjwWD17yTWeFKa0nMkes+QFbJVxpZD6y28FCm2WXtRmCOLCrt5xU3BUVTGreM/jU+NNdpjSBeLRHba4ayhPxWDzEimZ9e41j2uG5O82H8FHEfkQ3MVW8tclqd7SvkXy0DjVx/lSOLn1BZJ6etlDf2GLAZ5SMF5fa0CoI0o4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b=V809tkaj; arc=none smtp.client-ip=209.85.166.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20230601.gappssmtp.com header.i=@riscstar-com.20230601.gappssmtp.com header.b="V809tkaj" Received: by mail-io1-f44.google.com with SMTP id ca18e2360f4ac-8644aa73dfcso164166339f.0 for ; Tue, 13 May 2025 14:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1747173232; x=1747778032; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c92oi6wzBpfVhe8UTxXqXdvpyX/nmNAc/4aVrJYivQM=; b=V809tkajM9fdbQXPPnYe2Ga1cOQ1qM6E9SG+PFa5BvU9SkRGEJK7/vWPeSN/t1W6yn HI0HBHQgXepj4WXQzmBrXGFdrr2S8LReZmzPtyiAhsXwmMSvhfWZ4/EX4lEj6jvmTnjO cJpzyBAKNoFGbh1sU/rU6ujomE2HvIOzOzf4zrO7HTEgBPoCBrF+OPPeRt6TG1uuMxbE KGWzpTWVOCi5+RzMFO1Su5Yhh9UqhCT6hf+JJEfGWkw0zYSHD2aKjgYZ/Lp4klfrne99 pGKY1+ieoqYEPLD1sIp7yswE+iMV3adbgCj0qQ9BR2Z1/H6goFJAqpyr6RZYaW0y07Jk HZag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747173232; x=1747778032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c92oi6wzBpfVhe8UTxXqXdvpyX/nmNAc/4aVrJYivQM=; b=oszHuMvgfksiMCImbthqiJddR+alwokjatTogql5vdYiKooB+C9Wj18lKkXLDFgaZt sas1JPiCVvboHd2opGclLsRtw9rsMUaeFTQQMmp/d4gk8GjWZnpoOaGPZersgp3u9UqF b77StT3dM4AV4cOf+hkjGmkL9N5UUMyUZZOytJewZEZGuOa+DqcG+Llo3LAABg+5+duL RZzWWkn7w8P8XbrCBD7P+37VVCpD3p3NvbQ3c/J6EJSDKD4i8SBaWqBd/fPKxYQvaaqi eb6DmLasl9O2g6sWnD0vHtCkz6nxFVCpG3GkedlMAkTEOUkdLXidRJY+BtshZCcPHGYO awjg== X-Forwarded-Encrypted: i=1; AJvYcCWg4m9RqdqaCZmBaNkNc7Qvgs3qS7Ye6spW5yF6fMGtY382YdagUDyQpB3r6+8joCL2zv/zOl2Oww==@lists.linux.dev X-Gm-Message-State: AOJu0YxbmypYYetRNCfXk7rG++L/7qkTeVxxjOBmugAORRaMNJMZj+JY kfaeQJYWJtAzoZc2LGqKPZgN1hl3Mj+7tUS1VnDralDVycC0ALJWf7AK9kOiWmM= X-Gm-Gg: ASbGncupVc50euZqOPdd2rJ7VI0tI2LxQg4GpQNYSHOnQCjoRNoSyREFNIG6Hnabc2I wyHHi4fXHTchk8WGqxxTpB/aGqcdBijHGtRgC6xSxs6vjanhVJoTG4MnOYMoKye16Pw3XBTDL33 6PaDrlcUL+yHGRwgIw1WOyITRr6qu3YoHwv7dzeeR3XAofvSnXiPHteOXV5v+y6KY/TqV5LOEjX zKaCyDOP8pfmUu3708ZWrjKBcyfE38VpCtQ3ngDNZ+hwaRr+i/u8cKA+1wXNOpAp09ZtWbydJp9 TMalqkGGDo929T4AdNejPxUEopVGDuPayMwnJt1y2XqYumHmimQ2yiEtrfbVRFX1tDXjaCDAwzd o2ZXjclhxu43sKiRSf5yWUdjRJwkmnCPJpLM= X-Google-Smtp-Source: AGHT+IFXTVVUprs+T5AY0Es0gMzNRZGYiXxdAy9oyJxNDzYC3df/pMj+HsvNeDibG3/FsuEhR3x+Ag== X-Received: by 2002:a05:6602:4c0e:b0:862:ba37:eb0e with SMTP id ca18e2360f4ac-86a08e61362mr146647039f.12.1747173232233; Tue, 13 May 2025 14:53:52 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-867636e0dedsm239622539f.32.2025.05.13.14.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 May 2025 14:53:51 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dlan@gentoo.org Cc: heylenay@4d2.org, inochiama@outlook.com, guodong@riscstar.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 2/6] soc: spacemit: create a header for clock/reset registers Date: Tue, 13 May 2025 16:53:40 -0500 Message-ID: <20250513215345.3631593-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250513215345.3631593-1-elder@riscstar.com> References: <20250513215345.3631593-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: spacemit@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Move the definitions of register offsets and fields used by the SpacemiT K1 SoC CCUs into a separate header file, so that they can be shared by the reset driver that will be found under drivers/reset. Signed-off-by: Alex Elder Reviewed-by: Haylen Chu Reviewed-by: Yixun Lan --- drivers/clk/spacemit/ccu-k1.c | 111 +---------------------------- include/soc/spacemit/k1-syscon.h | 118 +++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 110 deletions(-) create mode 100644 include/soc/spacemit/k1-syscon.h diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cdde37a052353..801150f4ff0f5 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_pll.h" @@ -19,116 +20,6 @@ #include -/* APBS register offset */ -#define APBS_PLL1_SWCR1 0x100 -#define APBS_PLL1_SWCR2 0x104 -#define APBS_PLL1_SWCR3 0x108 -#define APBS_PLL2_SWCR1 0x118 -#define APBS_PLL2_SWCR2 0x11c -#define APBS_PLL2_SWCR3 0x120 -#define APBS_PLL3_SWCR1 0x124 -#define APBS_PLL3_SWCR2 0x128 -#define APBS_PLL3_SWCR3 0x12c - -/* MPMU register offset */ -#define MPMU_POSR 0x0010 -#define POSR_PLL1_LOCK BIT(27) -#define POSR_PLL2_LOCK BIT(28) -#define POSR_PLL3_LOCK BIT(29) -#define MPMU_SUCCR 0x0014 -#define MPMU_ISCCR 0x0044 -#define MPMU_WDTPCR 0x0200 -#define MPMU_RIPCCR 0x0210 -#define MPMU_ACGR 0x1024 -#define MPMU_APBCSCR 0x1050 -#define MPMU_SUCCR_1 0x10b0 - -/* APBC register offset */ -#define APBC_UART1_CLK_RST 0x00 -#define APBC_UART2_CLK_RST 0x04 -#define APBC_GPIO_CLK_RST 0x08 -#define APBC_PWM0_CLK_RST 0x0c -#define APBC_PWM1_CLK_RST 0x10 -#define APBC_PWM2_CLK_RST 0x14 -#define APBC_PWM3_CLK_RST 0x18 -#define APBC_TWSI8_CLK_RST 0x20 -#define APBC_UART3_CLK_RST 0x24 -#define APBC_RTC_CLK_RST 0x28 -#define APBC_TWSI0_CLK_RST 0x2c -#define APBC_TWSI1_CLK_RST 0x30 -#define APBC_TIMERS1_CLK_RST 0x34 -#define APBC_TWSI2_CLK_RST 0x38 -#define APBC_AIB_CLK_RST 0x3c -#define APBC_TWSI4_CLK_RST 0x40 -#define APBC_TIMERS2_CLK_RST 0x44 -#define APBC_ONEWIRE_CLK_RST 0x48 -#define APBC_TWSI5_CLK_RST 0x4c -#define APBC_DRO_CLK_RST 0x58 -#define APBC_IR_CLK_RST 0x5c -#define APBC_TWSI6_CLK_RST 0x60 -#define APBC_COUNTER_CLK_SEL 0x64 -#define APBC_TWSI7_CLK_RST 0x68 -#define APBC_TSEN_CLK_RST 0x6c -#define APBC_UART4_CLK_RST 0x70 -#define APBC_UART5_CLK_RST 0x74 -#define APBC_UART6_CLK_RST 0x78 -#define APBC_SSP3_CLK_RST 0x7c -#define APBC_SSPA0_CLK_RST 0x80 -#define APBC_SSPA1_CLK_RST 0x84 -#define APBC_IPC_AP2AUD_CLK_RST 0x90 -#define APBC_UART7_CLK_RST 0x94 -#define APBC_UART8_CLK_RST 0x98 -#define APBC_UART9_CLK_RST 0x9c -#define APBC_CAN0_CLK_RST 0xa0 -#define APBC_PWM4_CLK_RST 0xa8 -#define APBC_PWM5_CLK_RST 0xac -#define APBC_PWM6_CLK_RST 0xb0 -#define APBC_PWM7_CLK_RST 0xb4 -#define APBC_PWM8_CLK_RST 0xb8 -#define APBC_PWM9_CLK_RST 0xbc -#define APBC_PWM10_CLK_RST 0xc0 -#define APBC_PWM11_CLK_RST 0xc4 -#define APBC_PWM12_CLK_RST 0xc8 -#define APBC_PWM13_CLK_RST 0xcc -#define APBC_PWM14_CLK_RST 0xd0 -#define APBC_PWM15_CLK_RST 0xd4 -#define APBC_PWM16_CLK_RST 0xd8 -#define APBC_PWM17_CLK_RST 0xdc -#define APBC_PWM18_CLK_RST 0xe0 -#define APBC_PWM19_CLK_RST 0xe4 - -/* APMU register offset */ -#define APMU_JPG_CLK_RES_CTRL 0x020 -#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 -#define APMU_ISP_CLK_RES_CTRL 0x038 -#define APMU_LCD_CLK_RES_CTRL1 0x044 -#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 -#define APMU_LCD_CLK_RES_CTRL2 0x04c -#define APMU_CCIC_CLK_RES_CTRL 0x050 -#define APMU_SDH0_CLK_RES_CTRL 0x054 -#define APMU_SDH1_CLK_RES_CTRL 0x058 -#define APMU_USB_CLK_RES_CTRL 0x05c -#define APMU_QSPI_CLK_RES_CTRL 0x060 -#define APMU_DMA_CLK_RES_CTRL 0x064 -#define APMU_AES_CLK_RES_CTRL 0x068 -#define APMU_VPU_CLK_RES_CTRL 0x0a4 -#define APMU_GPU_CLK_RES_CTRL 0x0cc -#define APMU_SDH2_CLK_RES_CTRL 0x0e0 -#define APMU_PMUA_MC_CTRL 0x0e8 -#define APMU_PMU_CC2_AP 0x100 -#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -#define APMU_AUDIO_CLK_RES_CTRL 0x14c -#define APMU_HDMI_CLK_RES_CTRL 0x1b8 -#define APMU_CCI550_CLK_CTRL 0x300 -#define APMU_ACLK_CLK_CTRL 0x388 -#define APMU_CPU_C0_CLK_CTRL 0x38C -#define APMU_CPU_C1_CLK_CTRL 0x390 -#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc -#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 -#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc -#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -#define APMU_EMAC1_CLK_RES_CTRL 0x3ec - struct spacemit_ccu_data { struct clk_hw **hws; size_t num; diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h new file mode 100644 index 0000000000000..039a448c51a07 --- /dev/null +++ b/include/soc/spacemit/k1-syscon.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* SpacemiT clock and reset driver definitions for the K1 SoC */ + +#ifndef __SOC_K1_SYSCON_H__ +#define __SOC_K1_SYSCON_H__ + +/* APBS register offset */ +#define APBS_PLL1_SWCR1 0x100 +#define APBS_PLL1_SWCR2 0x104 +#define APBS_PLL1_SWCR3 0x108 +#define APBS_PLL2_SWCR1 0x118 +#define APBS_PLL2_SWCR2 0x11c +#define APBS_PLL2_SWCR3 0x120 +#define APBS_PLL3_SWCR1 0x124 +#define APBS_PLL3_SWCR2 0x128 +#define APBS_PLL3_SWCR3 0x12c + +/* MPMU register offset */ +#define MPMU_POSR 0x0010 +#define POSR_PLL1_LOCK BIT(27) +#define POSR_PLL2_LOCK BIT(28) +#define POSR_PLL3_LOCK BIT(29) +#define MPMU_SUCCR 0x0014 +#define MPMU_ISCCR 0x0044 +#define MPMU_WDTPCR 0x0200 +#define MPMU_RIPCCR 0x0210 +#define MPMU_ACGR 0x1024 +#define MPMU_APBCSCR 0x1050 +#define MPMU_SUCCR_1 0x10b0 + +/* APBC register offset */ +#define APBC_UART1_CLK_RST 0x00 +#define APBC_UART2_CLK_RST 0x04 +#define APBC_GPIO_CLK_RST 0x08 +#define APBC_PWM0_CLK_RST 0x0c +#define APBC_PWM1_CLK_RST 0x10 +#define APBC_PWM2_CLK_RST 0x14 +#define APBC_PWM3_CLK_RST 0x18 +#define APBC_TWSI8_CLK_RST 0x20 +#define APBC_UART3_CLK_RST 0x24 +#define APBC_RTC_CLK_RST 0x28 +#define APBC_TWSI0_CLK_RST 0x2c +#define APBC_TWSI1_CLK_RST 0x30 +#define APBC_TIMERS1_CLK_RST 0x34 +#define APBC_TWSI2_CLK_RST 0x38 +#define APBC_AIB_CLK_RST 0x3c +#define APBC_TWSI4_CLK_RST 0x40 +#define APBC_TIMERS2_CLK_RST 0x44 +#define APBC_ONEWIRE_CLK_RST 0x48 +#define APBC_TWSI5_CLK_RST 0x4c +#define APBC_DRO_CLK_RST 0x58 +#define APBC_IR_CLK_RST 0x5c +#define APBC_TWSI6_CLK_RST 0x60 +#define APBC_COUNTER_CLK_SEL 0x64 +#define APBC_TWSI7_CLK_RST 0x68 +#define APBC_TSEN_CLK_RST 0x6c +#define APBC_UART4_CLK_RST 0x70 +#define APBC_UART5_CLK_RST 0x74 +#define APBC_UART6_CLK_RST 0x78 +#define APBC_SSP3_CLK_RST 0x7c +#define APBC_SSPA0_CLK_RST 0x80 +#define APBC_SSPA1_CLK_RST 0x84 +#define APBC_IPC_AP2AUD_CLK_RST 0x90 +#define APBC_UART7_CLK_RST 0x94 +#define APBC_UART8_CLK_RST 0x98 +#define APBC_UART9_CLK_RST 0x9c +#define APBC_CAN0_CLK_RST 0xa0 +#define APBC_PWM4_CLK_RST 0xa8 +#define APBC_PWM5_CLK_RST 0xac +#define APBC_PWM6_CLK_RST 0xb0 +#define APBC_PWM7_CLK_RST 0xb4 +#define APBC_PWM8_CLK_RST 0xb8 +#define APBC_PWM9_CLK_RST 0xbc +#define APBC_PWM10_CLK_RST 0xc0 +#define APBC_PWM11_CLK_RST 0xc4 +#define APBC_PWM12_CLK_RST 0xc8 +#define APBC_PWM13_CLK_RST 0xcc +#define APBC_PWM14_CLK_RST 0xd0 +#define APBC_PWM15_CLK_RST 0xd4 +#define APBC_PWM16_CLK_RST 0xd8 +#define APBC_PWM17_CLK_RST 0xdc +#define APBC_PWM18_CLK_RST 0xe0 +#define APBC_PWM19_CLK_RST 0xe4 + +/* APMU register offset */ +#define APMU_JPG_CLK_RES_CTRL 0x020 +#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 +#define APMU_ISP_CLK_RES_CTRL 0x038 +#define APMU_LCD_CLK_RES_CTRL1 0x044 +#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 +#define APMU_LCD_CLK_RES_CTRL2 0x04c +#define APMU_CCIC_CLK_RES_CTRL 0x050 +#define APMU_SDH0_CLK_RES_CTRL 0x054 +#define APMU_SDH1_CLK_RES_CTRL 0x058 +#define APMU_USB_CLK_RES_CTRL 0x05c +#define APMU_QSPI_CLK_RES_CTRL 0x060 +#define APMU_DMA_CLK_RES_CTRL 0x064 +#define APMU_AES_CLK_RES_CTRL 0x068 +#define APMU_VPU_CLK_RES_CTRL 0x0a4 +#define APMU_GPU_CLK_RES_CTRL 0x0cc +#define APMU_SDH2_CLK_RES_CTRL 0x0e0 +#define APMU_PMUA_MC_CTRL 0x0e8 +#define APMU_PMU_CC2_AP 0x100 +#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 +#define APMU_AUDIO_CLK_RES_CTRL 0x14c +#define APMU_HDMI_CLK_RES_CTRL 0x1b8 +#define APMU_CCI550_CLK_CTRL 0x300 +#define APMU_ACLK_CLK_CTRL 0x388 +#define APMU_CPU_C0_CLK_CTRL 0x38C +#define APMU_CPU_C1_CLK_CTRL 0x390 +#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc +#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 +#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc +#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +#define APMU_EMAC1_CLK_RES_CTRL 0x3ec + +#endif /* __SOC_K1_SYSCON_H__ */ -- 2.45.2