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[89.182.129.90]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8d62422sm58498115e9.11.2026.05.13.00.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 00:20:07 -0700 (PDT) From: Andre Heider To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] riscv: dts: spacemit: k1-musepi-pro: enable PCIe ports Date: Wed, 13 May 2026 09:19:53 +0200 Message-ID: <20260513071958.29574-6-a.heider@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260513071958.29574-1-a.heider@gmail.com> References: <20260513071958.29574-1-a.heider@gmail.com> Precedence: bulk X-Mailing-List: spacemit@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Enable the two PCIe controllers along with their associated PHYs. They are routed to the M.2 M-key connector and to the PCIe slot. Signed-off-by: Andre Heider --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index b24b378b1b220..953c0ff6a0d34 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -36,6 +36,14 @@ led1 { }; }; + reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_vcc_4v0: regulator-vcc-4v0 { compatible = "regulator-fixed"; regulator-name = "VCC4V0"; @@ -272,6 +280,36 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_cfg>; -- 2.53.0