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Sat, 08 Aug 2026 06:22:01 -0700 (PDT) Date: Sat, 08 Aug 2026 21:21:57 +0800 Message-ID: From: Cody Kang To: Philipp Zabel Cc: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH RESEND 10/17] drm/spacemit: add Saturn DPU KMS pipeline In-Reply-To: <084a860a77f18aaafcda4b223eec4fdcd96e75c9.camel@pengutronix.de> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> <20260725-k3-display-v1-10-6de34d80e86c@gmail.com> <084a860a77f18aaafcda4b223eec4fdcd96e75c9.camel@pengutronix.de> Precedence: bulk X-Mailing-List: spacemit@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Hi Philipp, On Mon, 27 Jul 2026 09:35:38 +0200, Philipp Zabel wrote: > On Sa, 2026-07-25 at 00:51 -0400, Cody Kang via B4 Relay wrote: > > From: Cody Kang > > > > Add the atomic KMS implementation on top of the hardware backend: one > > CRTC and one primary plane per DPU instance. atomic_check validates > > the plane rectangle 1:1 against the mode and sizes the per-channel FBC > > line buffer; atomic commit builds the cmdlist batches, maps the > > framebuffer through the DMMU and arms the cfg-ready handshake, with > > vblank events driven from the DPU interrupt. > > > > Signed-off-by: Cody Kang > > --- > > drivers/gpu/drm/spacemit/spacemit_crtc.c | 815 +++++++++++++++++++++++++++++ > > drivers/gpu/drm/spacemit/spacemit_planes.c | 376 +++++++++++++ > > 2 files changed, 1191 insertions(+) > > > > diff --git a/drivers/gpu/drm/spacemit/spacemit_crtc.c b/drivers/gpu/drm/spacemit/spacemit_crtc.c > > new file mode 100644 > > index 000000000000..b75ff6320501 > > --- /dev/null > > +++ b/drivers/gpu/drm/spacemit/spacemit_crtc.c > > @@ -0,0 +1,815 @@ > [...] > > +/* > > + * The assert and deassert orders are not mirror images: the hardware wants > > + * these. > > + */ > > +static void dpu_reset_assert(struct device *dev, const char *name, > > + struct reset_control *rstc) > > +{ > > + int ret = reset_control_assert(rstc); > > + > > + if (ret) > > + dev_warn(dev, "failed to assert %s reset: %d\n", name, ret); > > +} > > + > > +static void dpu_reset_deassert(struct device *dev, const char *name, > > + struct reset_control *rstc) > > +{ > > + int ret = reset_control_deassert(rstc); > > + > > + if (ret) > > + dev_warn(dev, "failed to deassert %s reset: %d\n", name, ret); > > +} > > + > > +static int dpu_pm_suspend(struct device *dev) > > +{ > > + struct spacemit_drm_private *priv = dev_get_drvdata(dev); > > + struct spacemit_crtc *a_crtc = priv->a_crtc; > > + > > + /* > > + * Assert before gating: a reset asserted into an already-gated block > > + * has no clock edges to propagate on and leaves the register file > > + * untouched. > > + */ > > + dpu_reset_assert(dev, "lcd", a_crtc->lcd_reset); > > + dpu_reset_assert(dev, "esc", a_crtc->esc_reset); > > + dpu_reset_assert(dev, "mclk", a_crtc->mclk_reset); > > It looks like these three are mirrored, and could be handled by > reset_control_bulk_assert/deassert(). Thanks for the review. Indeed, reset_control_bulk_deassert() walking the array in reverse gives exactly the mirrored order the hardware wants. Will fix in v2. Cody