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X-CSE-ConnectionGUID: 72q6fz3tRq+JEmW+cu4qOQ== X-CSE-MsgGUID: CeuZD3VfRjiWoBOdE35tAQ== X-IronPort-AV: E=McAfee;i="6800,10657,11727"; a="62002476" X-IronPort-AV: E=Sophos;i="6.23,116,1770624000"; d="scan'208";a="62002476" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2026 08:52:23 -0700 X-CSE-ConnectionGUID: 5TwKcQXfRaGyUWJxFxtPTA== X-CSE-MsgGUID: p65BddDAQJO3Qoz1kXxlNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,116,1770624000"; d="scan'208";a="251356200" Received: from spandruv-desk1.amr.corp.intel.com (HELO [10.125.110.129]) ([10.125.110.129]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2026 08:52:23 -0700 Message-ID: <03a03ec8-4309-42ac-a13d-2fcc8396d547@intel.com> Date: Thu, 12 Mar 2026 08:52:37 -0700 Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu/centaur: Disable X86_FEATURE_FSGSBASE on Zhaoxin C4600 To: Tony W Wang-oc , me@ziyao.cc Cc: andrew.cooper3@citrix.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, linux-kernel@vger.kernel.org, mingo@redhat.com, stable@vger.kernel.org, tglx@kernel.org, x86@kernel.org, lukelin@viacpu.com, "TimGuo@zhaoxin.com" , cooperyan@zhaoxin.com, benjaminpan@viatech.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, "CobeChen@zhaoxin.com" References: <20260228173704.62460-1-me@ziyao.cc> <70139192-54e5-4a4b-bc96-1fe3ec4f7a0b@zhaoxin.com> <7d312ba6-58a0-48cb-92fa-d8094ddef21f@intel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 3/11/26 19:14, Tony W Wang-oc wrote: > > > +       if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping >= 14) { > +               native_rdmsr(0x1232, dummy, chip_pf); > +               chip_pf = (chip_pf >> 15) & 0x7; > +               c->microcode = intel_get_microcode_revision(); > + > +               if ((chip_pf == 0 && c->microcode < 0x20e) || > +                       (chip_pf == 1 && c->microcode < 0x208)) { > +                       pr_warn_once("CPU has broken FSGSBASE support; > clear FSGSBASE feature\n"); > +                       setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); > +               } > +       } So, I'm sorry but that's not really consistent how we're doing things these days. The model needs a symbolic name. The MSR you're reading is completely undocumented and unnamed. "chip_pf" is nonsensical and unexplained. Code is duplicated across the centaur and zhaoxin files. Once you have all of that fixed, you should have a simple: #define CENTAUR_MODEL_FOO VFM_MAKE(X86_VENDOR_CENTAUR, 6, 15) #define ZHAOXIN_MODEL_BAR VFM_MAKE(X86_VENDOR_ZHAOXIN, 6, 25) in a central header, plus: struct x86_cpu_id *naughty_list[] = { X86_MATCH_VFM_STEPS(CENTAUR_MODEL_FOO, 14, MAX_STEP, 0), X86_MATCH_VFM_STEPS(ZHAOXIN_MODEL_BAR, MIN_STEP, 3, 0), {} }; void check_fsgsbase_bugs() { u32 fixed_ucode; if (!cpu_feature_enabled(X86_FEATURE_FSGSBASE)) return; c = x86_match_cpu(naughty_list); if (!c) return; chip_pf = ... if (chip_pf == 0) fixed_ucode = 0x20e; if (chip_pf == 1) fixed_ucode = 0x208; if (intel_get_microcode_revision() >= fixed_ucode) return; pr_warn_once("Broken FSGSBASE support, clearing feature\n"); setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); } Then check_fsgsbase_bugs() can pretty much be called anywhere. It can even be in generic code. We are also getting some new matching fields in 'x86_cpu_id'. I suspect 'chip_pf' can be stored in there where Intel has the platform_id right now. But you don't have to do that now. Could you please go this route rather than copy-and-pasted chunks of code sprinkled with a healthy dose of magic numbers?