From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from manchmal.in-ulm.de ([217.10.9.201]:49715 "EHLO manchmal.in-ulm.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbbECIUW (ORCPT ); Sun, 3 May 2015 04:20:22 -0400 Date: Sun, 3 May 2015 10:20:19 +0200 From: Christoph Biedl To: Greg Kroah-Hartman Cc: stable@vger.kernel.org, "Evgeniy A. Dushistov" , Gregory CLEMENT , Linus Walleij Subject: Re: [PATCH 3.10 48/65] gpio: mvebu: Fix mask/unmask managment per irq chip type Message-ID: <1430641195@msgid.manchmal.in-ulm.de> Reply-To: stable@vger.kernel.org References: <20150502190114.555225285@linuxfoundation.org> <20150502190118.158065788@linuxfoundation.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="LZFKeWUZP29EKQNE" Content-Disposition: inline In-Reply-To: <20150502190118.158065788@linuxfoundation.org> Sender: stable-owner@vger.kernel.org List-ID: --LZFKeWUZP29EKQNE Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Greg Kroah-Hartman wrote... > From: Gregory CLEMENT >=20 > commit 61819549f572edd7fce53f228c0d8420cdc85f71 upstream. >=20 > Level IRQ handlers and edge IRQ handler are managed by tow different > sets of registers. But currently the driver uses the same mask for the > both registers. It lead to issues with the following scenario: (...) This results in a build breakage: (...) | CC drivers/gpio/gpio-mvebu.o | drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_edge_irq_mask': | drivers/gpio/gpio-mvebu.c:311:4: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c:313:2: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_edge_irq_unmask': | drivers/gpio/gpio-mvebu.c:326:4: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c:327:2: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_level_irq_mask': | drivers/gpio/gpio-mvebu.c:340:4: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c:341:2: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c: In function 'mvebu_gpio_level_irq_unmask': | drivers/gpio/gpio-mvebu.c:354:4: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' | drivers/gpio/gpio-mvebu.c:355:2: error: 'struct irq_chip_type' has no mem= ber named 'mask_cache_priv' Perhaps picking | commit 899f0e66fff36ebb6dd6a83af9aa631f6cb7e0dc | Author: Gerlando Falauto | Date: Mon May 6 14:30:19 2013 +0000 |=20 | genirq: Generic chip: Add support for per chip type mask cache will fix this but I couldn't check yet: My box is still busy test-building = the 3.14 series. Christoph --LZFKeWUZP29EKQNE Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAEBCgAGBQJVRdpCAAoJEMQsWOtZFJL993cQANVGOzA+fySSdNnbQdJV+EJN ecFHJ4bROTVupZA3MzG3qY7zu/GCQ1kldAo7YQd03W1/duh8CmO6WJqPaaMCFEUI Wp7HoVMhwbBJPmY8RrSo4EunuwYB3HmSMLgmWWq5LLtTw8V0gTiRoI+UBmtjhTYO ktK4uU590vSfZB+6fgVfZzCmOrkowDU0J5l3imVpPT9LEUGhCC1VtIprr6/6PbOs e7oMcoxU8Ofp3AGC9D44NHylnEo9e5OCn4sw8f+rLE/qEkikaBN8QpgHqcg827oV G/yn+y0+nSzkGH+2N2iTkicpdFOoV2VO0DKUfJDAeozCQb/Vrk7fh0gMts5/Al1r 1k3GvwpiMNnX99VWuYi5MCfBGz/UoMxkeDNO2F7Hw3dfRE48WxheKKERApC4FySI 4LgUtI6+zlHqDCuBWp2TmuUxfUHWuULUZoPiDtsrZFIs95APX4ps3vg60aHK/q0j wy76iKndcSal5eGANaUXcW97Mnfa8stCMLpKA4fHp/k/qk3rZ0zKrdvwQv7PGEF5 9gkX3n8yvWwMNB+ySIJSVj8VOzBK42U0QptXYT/CqmsBQFutUztdUpuLjSsmmSba D3vIcP7dPB50uTJFhvbe9alRyRoqld/4hlTHpvTqiCxISEmobVpG+JhnVtA+dVmj ZsCr6egZTvnD1DT4y2ti =BSHV -----END PGP SIGNATURE----- --LZFKeWUZP29EKQNE--