From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtprelay4.synopsys.com ([198.182.47.9]:55543 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754505AbbIKXcl (ORCPT ); Fri, 11 Sep 2015 19:32:41 -0400 From: Vineet Gupta To: Linus Torvalds CC: lkml , , Vineet Gupta , Subject: [PATCH] ARCv2: [axs103_smp] Reduce clk for SMP FPGA configs Date: Fri, 11 Sep 2015 16:32:22 -0700 Message-ID: <1442014342-5202-2-git-send-email-vgupta@synopsys.com> In-Reply-To: <1442014342-5202-1-git-send-email-vgupta@synopsys.com> References: <1442014342-5202-1-git-send-email-vgupta@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain Sender: stable-owner@vger.kernel.org List-ID: Newer bitfiles needs the reduced clk even for SMP builds Cc: #4.2 Signed-off-by: Vineet Gupta --- arch/arc/plat-axs10x/axs10x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index ad9825d4026a..0a77b19e1df8 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -402,6 +402,8 @@ static void __init axs103_early_init(void) unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; if (num_cores > 2) arc_set_core_freq(50 * 1000000); + else if (num_cores == 2) + arc_set_core_freq(75 * 1000000); #endif switch (arc_get_core_freq()/1000000) { -- 1.9.1