Patch "clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks" has been added to the 4.2-stable tree

Patch "clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks" has been added to the 4.2-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

to the 4.2-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-set-clk_set_rate_parent-on-ce1-clocks.patch
and it can be found in the queue-4.2 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From d7a304e9d018c99dda80f4c16ec0fe817b5be4a1 Mon Sep 17 00:00:00 2001
From: Stephen Boyd <sboyd@codeaurora.org>
Date: Tue, 14 Jul 2015 16:57:29 -0700
Subject: clk: qcom: Set CLK_SET_RATE_PARENT on ce1 clocks

From: Stephen Boyd <sboyd@codeaurora.org>

commit d7a304e9d018c99dda80f4c16ec0fe817b5be4a1 upstream.

The other ce clocks have the flag set, but ce1 doesn't, so
clk_set_rate() doesn't propagate up the tree to the ce1_src_clk.
Set the flag as this is supported.

Reported-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Tested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Fixes: 02824653200b ("clk: qcom: Add APQ8084 Global Clock Controller support")
Fixes: d33faa9ead8d ("clk: qcom: Add support for MSM8974's global clock controller (GCC)")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 drivers/clk/qcom/gcc-apq8084.c |    1 +
 drivers/clk/qcom/gcc-msm8974.c |    1 +
 2 files changed, 2 insertions(+)

--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -2105,6 +2105,7 @@ static struct clk_branch gcc_ce1_clk = {
 				"ce1_clk_src",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -1783,6 +1783,7 @@ static struct clk_branch gcc_ce1_clk = {
 				"ce1_clk_src",
 			},
 			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},


Patches currently in stable-queue which might be from sboyd@codeaurora.org are

queue-4.2/clk-exynos4-fix-wrong-clock-for-exynos4x12-adc.patch
queue-4.2/clk-rockchip-rk3288-add-clk_set_rate_parent-to-sclk_mac.patch
queue-4.2/clk-qcom-fix-msm8916-prng-clock-enable-bit.patch
queue-4.2/clk-qcom-set-clk_set_rate_parent-on-ce1-clocks.patch
queue-4.2/clk-versatile-off-by-one-in-clk_sp810_timerclken_of_get.patch
queue-4.2/clk-pxa-fix-core-frequency-reporting-unit.patch
queue-4.2/clk-pistachio-fix-32bit-integer-overflows.patch
queue-4.2/clk-pistachio-fix-override-of-clk-pll-settings-from-boot-loader.patch
queue-4.2/clk-pistachio-fix-pll-rate-calculation-in-integer-mode.patch
queue-4.2/clk-pistachio-correct-critical-clock-list.patch