From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com ([134.134.136.24]:1551 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752094AbbJGTI3 (ORCPT ); Wed, 7 Oct 2015 15:08:29 -0400 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Nick Bowler Subject: [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 Date: Wed, 7 Oct 2015 22:08:24 +0300 Message-Id: <1444244905-27894-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: From: Ville Syrjälä We accidentally lost the initial DPLL register write in 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M The "three times for luck" hack probably saved us from a total disaster. But anyway, bring the initial write back so that the code actually makes some sense. Cc: stable@vger.kernel.org Cc: Nick Bowler Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 147e700..f4fdff9 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); } + I915_WRITE(reg, dpll); + /* Wait for the clocks to stabilize. */ POSTING_READ(reg); udelay(150); -- 2.4.9