Patch "iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts" has been added to the 4.4-stable tree

Patch "iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts" has been added to the 4.4-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts

to the 4.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     iommu-vt-d-clear-ppr-bit-to-ensure-we-get-more-page-request-interrupts.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From 46924008273ed03bd11dbb32136e3da4cfe056e1 Mon Sep 17 00:00:00 2001
From: David Woodhouse <David.Woodhouse@intel.com>
Date: Mon, 15 Feb 2016 12:42:38 +0000
Subject: iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts

From: David Woodhouse <David.Woodhouse@intel.com>

commit 46924008273ed03bd11dbb32136e3da4cfe056e1 upstream.

According to the VT-d specification we need to clear the PPR bit in
the Page Request Status register when handling page requests, or the
hardware won't generate any more interrupts.

This wasn't actually necessary on SKL/KBL (which may well be the
subject of a hardware erratum, although it's harmless enough). But
other implementations do appear to get it right, and we only ever get
one interrupt unless we clear the PPR bit.

Reported-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 drivers/iommu/intel-svm.c   |    4 ++++
 include/linux/intel-iommu.h |    3 +++
 2 files changed, 7 insertions(+)

--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -524,6 +524,10 @@ static irqreturn_t prq_event_thread(int
 	struct intel_svm *svm = NULL;
 	int head, tail, handled = 0;
 
+	/* Clear PPR bit before reading head/tail registers, to
+	 * ensure that we get a new interrupt if needed. */
+	writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
+
 	tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 	head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 	while (head != tail) {
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -235,6 +235,9 @@ static inline void dmar_writeq(void __io
 /* low 64 bit */
 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
 
+/* PRS_REG */
+#define DMA_PRS_PPR	((u32)1)
+
 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)			\
 do {									\
 	cycles_t start_time = get_cycles();				\


Patches currently in stable-queue which might be from David.Woodhouse@intel.com are

queue-4.4/iommu-vt-d-fix-64-bit-accesses-to-32-bit-dmar_gsts_reg.patch
queue-4.4/iommu-vt-d-fix-mm-refcounting-to-hold-mm_count-not-mm_users.patch
queue-4.4/iommu-vt-d-clear-ppr-bit-to-ensure-we-get-more-page-request-interrupts.patch