From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com ([134.134.136.20]:11828 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752409AbcD0ITa (ORCPT ); Wed, 27 Apr 2016 04:19:30 -0400 Message-ID: <1461745167.30256.4.camel@sorvi> Subject: Re: [PATCH 1/3] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency From: Mika Kahola Reply-To: mika.kahola@intel.com To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Date: Wed, 27 Apr 2016 11:19:27 +0300 In-Reply-To: <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> References: <1461689194-6079-1-git-send-email-ville.syrjala@linux.intel.com> <1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: Indeed, BSpec says that this register should be programmed by CD clock minus one. Reviewed-by: Mika Kahola On Tue, 2016-04-26 at 19:46 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä > > Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure > if this is a late addition to the spec, or if I simply overlooked this > step when writing the original code. > > This is what Bspec has to say about CDCLK_FREQ: > "Program this field to the CD clock frequency minus one. This is used to > generate a divided down clock for miscellaneous timers in display." > > And the "Broadwell Sequences for Changing CD Clock Frequency" section > clarifies this further: > "For CD clock 337.5 MHz, program 337 decimal. > For CD clock 450 MHz, program 449 decimal. > For CD clock 540 MHz, program 539 decimal. > For CD clock 675 MHz, program 674 decimal." > > Cc: stable@vger.kernel.org > Cc: Mika Kahola > Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support") > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 03264fd30fdd..41c9ae03652b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7484,6 +7484,8 @@ enum skl_disp_power_wells { > #define TRANS_CLK_SEL_DISABLED (0x0<<29) > #define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29) > > +#define CDCLK_FREQ _MMIO(0x46200) > + > #define _TRANSA_MSA_MISC 0x60410 > #define _TRANSB_MSA_MISC 0x61410 > #define _TRANSC_MSA_MISC 0x62410 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 929fd93b3e5d..ea55dd331fac 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9647,6 +9647,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) > sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); > mutex_unlock(&dev_priv->rps.hw_lock); > > + I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); > + > intel_update_cdclk(dev); > > WARN(cdclk != dev_priv->cdclk_freq, -- Mika Kahola - Intel OTC