From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com ([192.55.52.120]:20948 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755500AbcEFD1G (ORCPT ); Thu, 5 May 2016 23:27:06 -0400 From: yu.c.chen@intel.com To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Bin Gao , Len Brown , "Rafael J. Wysocki" , Chen Yu , "3 . 14+ # 3 . 14+" Subject: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay Date: Fri, 6 May 2016 11:33:39 +0800 Message-Id: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com> Sender: stable-owner@vger.kernel.org List-ID: From: Chen Yu Currently we fetch the tsc radio by: ratio = (lo >> 8) & 0x1f; thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according to Intel 64 and IA-32 Architectures Software Developer Manual 35.5, the ratio bit should be bit8~bit15, otherwise we might get incorrect tsc ratio and cause system hang later(mdelay corrupted). Fix this problem by masking 0xff instead. Cc: 3.14+ # 3.14+ Signed-off-by: Chen Yu --- arch/x86/kernel/tsc_msr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c index 92ae6ac..6aa0f4d 100644 --- a/arch/x86/kernel/tsc_msr.c +++ b/arch/x86/kernel/tsc_msr.c @@ -92,7 +92,7 @@ unsigned long try_msr_calibrate_tsc(void) if (freq_desc_tables[cpu_index].msr_plat) { rdmsr(MSR_PLATFORM_INFO, lo, hi); - ratio = (lo >> 8) & 0x1f; + ratio = (lo >> 8) & 0xff; } else { rdmsr(MSR_IA32_PERF_STATUS, lo, hi); ratio = (hi >> 8) & 0x1f; -- 2.7.4