From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:51964 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756722AbcEFRnl (ORCPT ); Fri, 6 May 2016 13:43:41 -0400 Subject: Patch "clk: qcom: msm8960: Fix ce3_src register offset" has been added to the 4.5-stable tree To: sboyd@codeaurora.org, bjorn.andersson@linaro.org, gregkh@linuxfoundation.org, srinivas.kandagatla@linaro.org Cc: , From: Date: Fri, 06 May 2016 12:30:14 -0400 Message-ID: <146255221477195@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: qcom: msm8960: Fix ce3_src register offset to the 4.5-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-qcom-msm8960-fix-ce3_src-register-offset.patch and it can be found in the queue-4.5 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 0f75e1a370fd843c9e508fc1ccf0662833034827 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 1 Mar 2016 17:26:48 -0800 Subject: clk: qcom: msm8960: Fix ce3_src register offset From: Stephen Boyd commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream. The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla Tested-by: Bjorn Andersson Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman --- drivers/clk/qcom/gcc-msm8960.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2753,7 +2753,7 @@ static struct clk_rcg ce3_src = { }, .freq_tbl = clk_tbl_ce3, .clkr = { - .enable_reg = 0x2c08, + .enable_reg = 0x36c0, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "ce3_src", Patches currently in stable-queue which might be from sboyd@codeaurora.org are queue-4.5/clk-bcm2835-fix-check-of-error-code-returned-by-devm_ioremap_resource.patch queue-4.5/clk-qcom-msm8960-fix-ce3_src-register-offset.patch queue-4.5/clk-versatile-sp810-support-reentrance.patch queue-4.5/clk-divider-make-sure-read-only-dividers-do-not-write-to-their-register.patch queue-4.5/clk-xgene-add-missing-parenthesis-when-clearing-divider-value.patch queue-4.5/clk-qcom-msm8960-fix-ce3_core-clk-enable-register.patch queue-4.5/clk-meson-fix-meson_clk_register_clks-signature-type-mismatch.patch