From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:50451 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758684AbcEFR2T (ORCPT ); Fri, 6 May 2016 13:28:19 -0400 Subject: Patch "clk: sunxi: Fix sun8i-a23-apb0-clk divider flags" has been added to the 4.5-stable tree To: wens@csie.org, gregkh@linuxfoundation.org, maxime.ripard@free-electrons.com Cc: , From: Date: Fri, 06 May 2016 12:30:17 -0400 Message-ID: <1462552217230230@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: sunxi: Fix sun8i-a23-apb0-clk divider flags to the 4.5-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-sunxi-fix-sun8i-a23-apb0-clk-divider-flags.patch and it can be found in the queue-4.5 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 33f60d02605a3a604e56b07a78d80d7d801b2843 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 15 Feb 2016 17:40:19 +0800 Subject: clk: sunxi: Fix sun8i-a23-apb0-clk divider flags From: Chen-Yu Tsai commit 33f60d02605a3a604e56b07a78d80d7d801b2843 upstream. The APB0 clock on A23 is a zero-based divider, not a power-of-two based divider. Note that this patch does not apply cleanly to kernels before 4.5-rc1, which added CLK_OF_DECLARE support to this driver. Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Greg Kroah-Hartman --- drivers/clk/sunxi/clk-sun8i-apb0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/sunxi/clk-sun8i-apb0.c +++ b/drivers/clk/sunxi/clk-sun8i-apb0.c @@ -36,7 +36,7 @@ static struct clk *sun8i_a23_apb0_regist /* The A23 APB0 clock is a standard 2 bit wide divider clock */ clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg, - 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL); + 0, 2, 0, NULL); if (IS_ERR(clk)) return clk; Patches currently in stable-queue which might be from wens@csie.org are queue-4.5/clk-sunxi-fix-sun8i-a23-apb0-clk-divider-flags.patch