From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:33198 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751089AbcFDTQG (ORCPT ); Sat, 4 Jun 2016 15:16:06 -0400 Subject: Patch "clk: bcm2835: Fix PLL poweron" has been added to the 4.5-stable tree To: eric@anholt.net, gregkh@linuxfoundation.org, sboyd@codeaurora.org Cc: , From: Date: Sat, 04 Jun 2016 12:16:05 -0700 Message-ID: <1465067765104196@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: bcm2835: Fix PLL poweron to the 4.5-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-bcm2835-fix-pll-poweron.patch and it can be found in the queue-4.5 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From e708b383f4b94feca2e0d5d06e1cfc13cdfea100 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 13 Apr 2016 13:05:03 -0700 Subject: clk: bcm2835: Fix PLL poweron From: Eric Anholt commit e708b383f4b94feca2e0d5d06e1cfc13cdfea100 upstream. In poweroff, we set the reset bit and the power down bit, but only managed to unset the reset bit for poweron. This meant that if HDMI did -EPROBE_DEFER after it had grabbed its clocks, we'd power down the PLLH (that had been on at boot time) and never recover. Signed-off-by: Eric Anholt Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman --- drivers/clk/bcm/clk-bcm2835.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -911,6 +911,10 @@ static int bcm2835_pll_on(struct clk_hw const struct bcm2835_pll_data *data = pll->data; ktime_t timeout; + cprman_write(cprman, data->a2w_ctrl_reg, + cprman_read(cprman, data->a2w_ctrl_reg) & + ~A2W_PLL_CTRL_PWRDN); + /* Take the PLL out of reset. */ cprman_write(cprman, data->cm_ctrl_reg, cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); Patches currently in stable-queue which might be from eric@anholt.net are queue-4.5/clk-bcm2835-correctly-enable-fractional-clock-support.patch queue-4.5/clk-bcm2835-pll_off-should-only-update-cm_pll_anarst.patch queue-4.5/clk-bcm2835-fix-pll-poweron.patch queue-4.5/clk-bcm2835-divider-value-has-to-be-1-or-more.patch