From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:60225 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1945958AbcHRK5r (ORCPT ); Thu, 18 Aug 2016 06:57:47 -0400 Subject: Patch "clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits" has been added to the 4.7-stable tree To: zhengxing@rock-chips.com, gregkh@linuxfoundation.org, heiko@sntech.de, zyw@rock-chips.com Cc: , From: Date: Thu, 18 Aug 2016 12:57:36 +0200 Message-ID: <147151785618544@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits to the 4.7-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-rockchip-fix-incorrect-rk3399-spdif-dptx-divider-bits.patch and it can be found in the queue-4.7 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 3770821fa360525e6c726cd562a2438a0aa5d566 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Thu, 30 Jun 2016 10:18:59 +0800 Subject: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits From: Xing Zheng commit 3770821fa360525e6c726cd562a2438a0aa5d566 upstream. The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Reported-by: Chris Zhong Tested-by: Chris Zhong Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399 RK3399_CLKGATE_CON(8), 15, GFLAGS), COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0, - RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS, + RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, RK3399_CLKGATE_CON(10), 6, GFLAGS), /* i2s */ COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0, Patches currently in stable-queue which might be from zhengxing@rock-chips.com are queue-4.7/clk-rockchip-fix-incorrect-rk3399-spdif-dptx-divider-bits.patch