From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:34199 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750882AbcIINia (ORCPT ); Fri, 9 Sep 2016 09:38:30 -0400 Subject: Patch "[PATCH 017/135] clk: xgene: Fix divider with non-zero shift value" has been added to the 4.4-stable tree To: lho@apm.com, alexander.levin@verizon.com, gregkh@linuxfoundation.org, sboyd@codeaurora.org Cc: , From: Date: Fri, 09 Sep 2016 15:37:52 +0200 Message-ID: <147342827289165@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled [PATCH 017/135] clk: xgene: Fix divider with non-zero shift value to the 4.4-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: 0017-clk-xgene-Fix-divider-with-non-zero-shift-value.patch and it can be found in the queue-4.4 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From a9a06362673e662cf7a194d37388b409a4e1abbc Mon Sep 17 00:00:00 2001 From: Loc Ho Date: Thu, 19 Nov 2015 12:20:30 -0700 Subject: [PATCH 017/135] clk: xgene: Fix divider with non-zero shift value [ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ] The X-Gene clock driver missed the divider shift operation when set the divider value. Signed-off-by: Loc Ho Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/clk/clk-xgene.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk /* Set new divider */ data = xgene_clk_read(pclk->param.divider_reg + pclk->param.reg_divider_offset); - data &= ~((1 << pclk->param.reg_divider_width) - 1); + data &= ~((1 << pclk->param.reg_divider_width) - 1) + << pclk->param.reg_divider_shift; data |= divider; xgene_clk_write(data, pclk->param.divider_reg + pclk->param.reg_divider_offset); Patches currently in stable-queue which might be from lho@apm.com are queue-4.4/0017-clk-xgene-Fix-divider-with-non-zero-shift-value.patch