From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk0-f196.google.com ([209.85.220.196]:34840 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751638AbcIINpF (ORCPT ); Fri, 9 Sep 2016 09:45:05 -0400 Received: by mail-qk0-f196.google.com with SMTP id w204so5724612qka.2 for ; Fri, 09 Sep 2016 06:45:05 -0700 (PDT) From: Fabio Estevam To: stable@vger.kernel.org Cc: marc.zyngier@arm.com, Fabio Estevam Subject: [PATCH v2] irqchip/gic: Allow self-SGIs for SMP on UP configurations Date: Fri, 9 Sep 2016 10:44:42 -0300 Message-Id: <1473428682-14552-1-git-send-email-festevam@gmail.com> Sender: stable-owner@vger.kernel.org List-ID: From: Marc Zyngier commit 059e232089e45b0befc9933d31209c225e08b426 upstream. On systems where a single CPU is present, the GIC may not support having SGIs delivered to a target list. In that case, we use the self-SGI mechanism to allow the interrupt to be delivered locally. Cc: # 4.7.x Tested-by: Fabio Estevam Signed-off-by: Marc Zyngier Signed-off-by: Fabio Estevam --- Changes since v1: - Add the 4.7.x notation drivers/irqchip/irq-gic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index c2cab57..390fac5 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -769,6 +769,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) int cpu; unsigned long flags, map = 0; + if (unlikely(nr_cpu_ids == 1)) { + /* Only one CPU? let's do a self-IPI... */ + writel_relaxed(2 << 24 | irq, + gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); + return; + } + raw_spin_lock_irqsave(&irq_controller_lock, flags); /* Convert our logical CPU mask into a physical one. */ -- 1.9.1