From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ducie-dc1.codethink.co.uk ([185.25.241.215]:41336 "EHLO ducie-dc1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755290AbcITQ0G (ORCPT ); Tue, 20 Sep 2016 12:26:06 -0400 Message-ID: <1474388761.31504.27.camel@codethink.co.uk> Subject: Re: [PATCH 4.4 017/192] [PATCH 017/135] clk: xgene: Fix divider with non-zero shift value From: Ben Hutchings To: Loc Ho , Greg Kroah-Hartman Cc: Linux Kernel Mailing List , stable@vger.kernel.org, Stephen Boyd , Sasha Levin Date: Tue, 20 Sep 2016 17:26:01 +0100 In-Reply-To: References: <20160912152158.855601725@linuxfoundation.org> <20160912152159.629267769@linuxfoundation.org> <1474371589.31504.4.camel@codethink.co.uk> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: stable-owner@vger.kernel.org List-ID: On Tue, 2016-09-20 at 09:07 -0700, Loc Ho wrote: > Hi, > > >> 4.4-stable review patch. If anyone has any objections, please let me know. > >> > >> ------------------ > >> > >> [ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ] > >> > >> The X-Gene clock driver missed the divider shift operation when > >> set the divider value. > >> > >> Signed-off-by: Loc Ho > >> Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") > >> Signed-off-by: Stephen Boyd > >> Signed-off-by: Sasha Levin > >> Signed-off-by: Greg Kroah-Hartman > >> --- > >> drivers/clk/clk-xgene.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> --- a/drivers/clk/clk-xgene.c > >> +++ b/drivers/clk/clk-xgene.c > >> @@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk > >> /* Set new divider */ > >> data = xgene_clk_read(pclk->param.divider_reg + > >> pclk->param.reg_divider_offset); > >> - data &= ~((1 << pclk->param.reg_divider_width) - 1); > >> + data &= ~((1 << pclk->param.reg_divider_width) - 1) > >> + << pclk->param.reg_divider_shift; > > [...] > > > > This still does the wrong thing when the shift value is non-zero: it > > clears all bits to the right of the divider field in data. I think the > > correct assignment is: > > > > data &= ~(((1 << pclk->param.reg_divider_width) - 1) > > << pclk->param.reg_divider_shift); > > > > Yes... There was an later patch that address this - > https://patchwork.kernel.org/patch/8458361 But it didn't go into this stable update, because you didn't point that out during review. Greg, the upstream commit is: commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605 Author: Loc Ho Date: Mon Feb 29 14:15:43 2016 -0700 clk: xgene: Add missing parenthesis when clearing divider value Ben. -- Ben Hutchings Software Developer, Codethink Ltd.