From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:35515 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932932AbcJYS6O (ORCPT ); Tue, 25 Oct 2016 14:58:14 -0400 Subject: Patch "PCI: tegra: Fix argument order in tegra_pcie_phy_disable()" has been added to the 4.7-stable tree To: bhelgaas@google.com, gregkh@linuxfoundation.org, treding@nvidia.com Cc: , From: Date: Tue, 25 Oct 2016 20:57:43 +0200 Message-ID: <147742186313235@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled PCI: tegra: Fix argument order in tegra_pcie_phy_disable() to the 4.7-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pci-tegra-fix-argument-order-in-tegra_pcie_phy_disable.patch and it can be found in the queue-4.7 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 8dd99bca7bfa4b62753b556c45d26f45ec9da6e6 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 5 Oct 2016 16:04:13 -0500 Subject: PCI: tegra: Fix argument order in tegra_pcie_phy_disable() From: Bjorn Helgaas commit 8dd99bca7bfa4b62753b556c45d26f45ec9da6e6 upstream. The tegra_pcie_phy_disable() path called pads_writel() with arguments in the wrong order. Swap them to be the "value, offset" order expected by pads_writel(). Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs") Signed-off-by: Bjorn Helgaas Acked-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -877,7 +877,7 @@ static int tegra_pcie_phy_disable(struct /* override IDDQ */ value = pads_readl(pcie, PADS_CTL); value |= PADS_CTL_IDDQ_1L; - pads_writel(pcie, PADS_CTL, value); + pads_writel(pcie, value, PADS_CTL); /* reset PLL */ value = pads_readl(pcie, soc->pads_pll_ctl); Patches currently in stable-queue which might be from bhelgaas@google.com are queue-4.7/pci-mark-atheros-ar9580-to-avoid-bus-reset.patch queue-4.7/pci-tegra-fix-argument-order-in-tegra_pcie_phy_disable.patch