From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:48274 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751702AbcJ2NUB (ORCPT ); Sat, 29 Oct 2016 09:20:01 -0400 Subject: Patch "clk: gcc-msm8996: Fix pcie 2 pipe register offset" has been added to the 4.8-stable tree To: srinivas.kandagatla@linaro.org, gregkh@linuxfoundation.org, sboyd@codeaurora.org Cc: , From: Date: Sat, 29 Oct 2016 09:20:04 -0400 Message-ID: <147774720466147@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: gcc-msm8996: Fix pcie 2 pipe register offset to the 4.8-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-gcc-msm8996-fix-pcie-2-pipe-register-offset.patch and it can be found in the queue-4.8 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From ce61966c05f276294b6be04d1765ad0d827ddefd Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 25 Aug 2016 12:20:46 +0100 Subject: clk: gcc-msm8996: Fix pcie 2 pipe register offset From: Srinivas Kandagatla commit ce61966c05f276294b6be04d1765ad0d827ddefd upstream. This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman --- drivers/clk/qcom/gcc-msm8996.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_ }; static struct clk_branch gcc_pcie_2_pipe_clk = { - .halt_reg = 0x6e108, + .halt_reg = 0x6e018, .clkr = { - .enable_reg = 0x6e108, + .enable_reg = 0x6e018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk", Patches currently in stable-queue which might be from srinivas.kandagatla@linaro.org are queue-4.8/clk-gcc-msm8996-fix-pcie-2-pipe-register-offset.patch queue-4.8/clk-qcom-select-gdsc-for-msm8996-gcc-and-mmcc.patch