From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk0-f196.google.com ([209.85.220.196]:33370 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752344AbcKTXbJ (ORCPT ); Sun, 20 Nov 2016 18:31:09 -0500 Received: by mail-qk0-f196.google.com with SMTP id x190so43431033qkb.0 for ; Sun, 20 Nov 2016 15:31:08 -0800 (PST) From: Fabio Estevam To: stable@vger.kernel.org Cc: sboyd@codeaurora.org, emil@limesaudio.com, shawnguo@kernel.org, Anson Huang , Fabio Estevam Subject: [PATCH] clk: imx: fix integer overflow in AV PLL round rate Date: Sun, 20 Nov 2016 21:30:55 -0200 Message-Id: <1479684655-23033-1-git-send-email-festevam@gmail.com> Sender: stable-owner@vger.kernel.org List-ID: From: Emil Lundmark [commit 5c2f117a22e46a4afee6ddee29b653a7a2a6b41f upstream] Since 'parent_rate * mfn' may overflow 32 bits, the result should be stored using 64 bits. The problem was discovered when trying to set the rate of the audio PLL (pll4_post_div) on an i.MX6Q. The desired rate was 196.608 MHz, but the actual rate returned was 192.000570 MHz. The round rate function should have been able to return 196.608 MHz, i.e., the desired rate. Cc: # 4.8.x Fixes: ba7f4f557eb6 ("clk: imx: correct AV PLL rate formula") Cc: Anson Huang Signed-off-by: Emil Lundmark Reviewed-by: Fabio Estevam Acked-by: Shawn Guo Signed-off-by: Stephen Boyd Signed-off-by: Fabio Estevam --- drivers/clk/imx/clk-pllv3.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index 19f9b62..7a6acc3 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -223,7 +223,7 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, temp64 *= mfn; do_div(temp64, mfd); - return (parent_rate * div) + (u32)temp64; + return parent_rate * div + (unsigned long)temp64; } static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, @@ -247,7 +247,11 @@ static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, do_div(temp64, parent_rate); mfn = temp64; - return parent_rate * div + parent_rate * mfn / mfd; + temp64 = (u64)parent_rate; + temp64 *= mfn; + do_div(temp64, mfd); + + return parent_rate * div + (unsigned long)temp64; } static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, -- 2.7.4