From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:45792 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751385AbdH0M4I (ORCPT ); Sun, 27 Aug 2017 08:56:08 -0400 Subject: Patch "drm: rcar-du: Fix display timing controller parameter" has been added to the 4.9-stable tree To: koji.matsuoka.xm@renesas.com, gregkh@linuxfoundation.org, laurent.pinchart+renesas@ideasonboard.com, nhan.nguyen.yb@renesas.com, thong.ho.px@rvc.renesas.com Cc: , From: Date: Sun, 27 Aug 2017 14:56:05 +0200 Message-ID: <150383856568150@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled drm: rcar-du: Fix display timing controller parameter to the 4.9-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: drm-rcar-du-fix-display-timing-controller-parameter.patch and it can be found in the queue-4.9 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Mon, 18 Apr 2016 16:31:30 +0900 Subject: drm: rcar-du: Fix display timing controller parameter From: Koji Matsuoka commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 upstream. There is a bug in the setting of the DES (Display Enable Signal) register. This current setting occurs 1 dot left shift. The DES register should be set minus one value about the specifying value with H/W specification. This patch corrects it. Signed-off-by: Koji Matsuoka Signed-off-by: Laurent Pinchart Signed-off-by: Thong Ho Signed-off-by: Nhan Nguyen Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -172,7 +172,7 @@ static void rcar_du_crtc_set_display_tim mode->crtc_vsync_start - 1); rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); - rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start); + rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); } Patches currently in stable-queue which might be from koji.matsuoka.xm@renesas.com are queue-4.9/drm-rcar-du-fix-h-v-sync-signal-polarity-configuration.patch queue-4.9/drm-rcar-du-fix-display-timing-controller-parameter.patch