From: <gregkh@linuxfoundation.org>
To: xiong.y.zhang@intel.com, gregkh@linuxfoundation.org,
zhenyuw@linux.intel.com
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition" has been added to the 4.14-stable tree
Date: Mon, 04 Dec 2017 15:01:54 +0100 [thread overview]
Message-ID: <15123961141834@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-gvt-correct-addr_4k-2m-1g_mask-definition.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From b721b65af4eb46df6a1d9e34b14003225e403565 Mon Sep 17 00:00:00 2001
From: Xiong Zhang <xiong.y.zhang@intel.com>
Date: Tue, 28 Nov 2017 07:29:54 +0800
Subject: drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition
From: Xiong Zhang <xiong.y.zhang@intel.com>
commit b721b65af4eb46df6a1d9e34b14003225e403565 upstream.
For ADDR_4K_MASK, bit[45..12] should be 1, all other bits
should be 0. The current definition wrongly set bit[46] as 1
also. This path fixes this.
v2: Add commit message, fixes and cc stable.(Zhenyu)
Fixes: 2707e4446688("drm/i915/gvt: vGPU graphics memory virtualization")
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/gpu/drm/i915/gvt/gtt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -311,9 +311,9 @@ static inline int gtt_set_entry64(void *
#define GTT_HAW 46
-#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
-#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
-#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
+#define ADDR_1G_MASK (((1UL << (GTT_HAW - 30)) - 1) << 30)
+#define ADDR_2M_MASK (((1UL << (GTT_HAW - 21)) - 1) << 21)
+#define ADDR_4K_MASK (((1UL << (GTT_HAW - 12)) - 1) << 12)
static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry *e)
{
Patches currently in stable-queue which might be from xiong.y.zhang@intel.com are
queue-4.14/drm-i915-gvt-correct-addr_4k-2m-1g_mask-definition.patch
reply other threads:[~2017-12-04 14:01 UTC|newest]
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