From: <gregkh@linuxfoundation.org>
To: zhongkaihua@huawei.com, alexander.levin@verizon.com,
gregkh@linuxfoundation.org, guodong.xu@linaro.org,
sboyd@codeaurora.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: hi3660: fix incorrect uart3 clock freqency" has been added to the 4.14-stable tree
Date: Tue, 12 Dec 2017 11:11:16 +0100 [thread overview]
Message-ID: <151307347610456@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: hi3660: fix incorrect uart3 clock freqency
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-hi3660-fix-incorrect-uart3-clock-freqency.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Tue Dec 12 10:32:42 CET 2017
From: Zhong Kaihua <zhongkaihua@huawei.com>
Date: Mon, 7 Aug 2017 22:51:56 +0800
Subject: clk: hi3660: fix incorrect uart3 clock freqency
From: Zhong Kaihua <zhongkaihua@huawei.com>
[ Upstream commit d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8 ]
UART3 clock rate is doubled in previous commit.
This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.
This patch changes clock source rate of clk_factor_uart3 to 100000000.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/hisilicon/clk-hi3660.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_cloc
/* crgctrl */
static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
- { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, },
+ { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
{ HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
{ HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
{ HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
Patches currently in stable-queue which might be from zhongkaihua@huawei.com are
queue-4.14/clk-hi3660-fix-incorrect-uart3-clock-freqency.patch
reply other threads:[~2017-12-12 10:11 UTC|newest]
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