From: <gregkh@linuxfoundation.org>
To: yamada.masahiro@socionext.com, alexander.levin@verizon.com,
gregkh@linuxfoundation.org, sboyd@codeaurora.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: uniphier: fix DAPLL2 clock rate of Pro5" has been added to the 4.9-stable tree
Date: Tue, 12 Dec 2017 13:33:20 +0100 [thread overview]
Message-ID: <151308200015101@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: uniphier: fix DAPLL2 clock rate of Pro5
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-uniphier-fix-dapll2-clock-rate-of-pro5.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Tue Dec 12 13:26:17 CET 2017
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 5 Oct 2017 11:32:59 +0900
Subject: clk: uniphier: fix DAPLL2 clock rate of Pro5
From: Masahiro Yamada <yamada.masahiro@socionext.com>
[ Upstream commit 67affb78a4e4feb837953e3434c8402a5c3b272f ]
The parent of DAPLL2 should be DAPLL1. Fix the clock connection.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -98,7 +98,7 @@ const struct uniphier_clk_data uniphier_
const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
- UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */
+ UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
UNIPHIER_PRO5_SYS_CLK_SD,
Patches currently in stable-queue which might be from yamada.masahiro@socionext.com are
queue-4.9/clk-uniphier-fix-dapll2-clock-rate-of-pro5.patch
queue-4.9/kbuild-do-not-call-cc-option-before-kbuild_cflags-initialization.patch
queue-4.9/coccinelle-fix-parallel-build-with-check-scripts-coccicheck.patch
queue-4.9/kbuild-pkg-use-transform-option-to-prefix-paths-in-tar.patch
reply other threads:[~2017-12-12 12:33 UTC|newest]
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