Patch "clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider" has been added to the 4.14-stable tree

Patch "clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider" has been added to the 4.14-stable tree

[gregkh]

This is a note to let you know that I've just added the patch titled

    clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider

to the 4.14-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-sunxi-ng-sun5i-fix-bit-offset-of-audio-pll-post-divider.patch
and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.


>From foo@baz Wed Dec 20 18:17:52 CET 2017
From: Chen-Yu Tsai <wens@csie.org>
Date: Thu, 12 Oct 2017 16:36:57 +0800
Subject: clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider

From: Chen-Yu Tsai <wens@csie.org>


[ Upstream commit d51fe3ba9773c8b6fc79f82bbe75d64baf604292 ]

The post-divider for the audio PLL is in bits [29:26], as specified
in the user manual, not [19:16] as currently programmed in the code.
The post-divider has a default register value of 2, i.e. a divider
of 3. This means the clock rate fed to the audio codec would be off.

This was discovered when porting sigma-delta modulation for the PLL
to sun5i, which needs the post-divider to be 1.

Fix the bit offset, so we do actually force the post-divider to a
certain value.

Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/clk/sunxi-ng/ccu-sun5i.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -982,8 +982,8 @@ static void __init sun5i_ccu_init(struct
 
 	/* Force the PLL-Audio-1x divider to 4 */
 	val = readl(reg + SUN5I_PLL_AUDIO_REG);
-	val &= ~GENMASK(19, 16);
-	writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG);
+	val &= ~GENMASK(29, 26);
+	writel(val | (3 << 26), reg + SUN5I_PLL_AUDIO_REG);
 
 	/*
 	 * Use the peripheral PLL as the AHB parent, instead of CPU /


Patches currently in stable-queue which might be from wens@csie.org are

queue-4.14/clk-sunxi-ng-nm-check-if-requested-rate-is-supported-by-fractional-clock.patch
queue-4.14/clk-sunxi-ng-sun6i-rename-hdmi-ddc-clock-to-avoid-name-collision.patch
queue-4.14/clk-sunxi-ng-sun5i-fix-bit-offset-of-audio-pll-post-divider.patch