From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:54272 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751063AbdLaKOP (ORCPT ); Sun, 31 Dec 2017 05:14:15 -0500 Subject: Patch "net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY" has been added to the 4.14-stable tree To: f.fainelli@gmail.com, davem@davemloft.net, gregkh@linuxfoundation.org Cc: , From: Date: Sun, 31 Dec 2017 11:14:01 +0100 Message-ID: <151471524146131@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY to the 4.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: net-dsa-bcm_sf2-clear-iddq_global_pwr-bit-for-phy.patch and it can be found in the queue-4.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From foo@baz Sun Dec 31 11:12:48 CET 2017 From: Florian Fainelli Date: Tue, 21 Nov 2017 17:37:46 -0800 Subject: net: dsa: bcm_sf2: Clear IDDQ_GLOBAL_PWR bit for PHY From: Florian Fainelli [ Upstream commit 4b52d010113e11006a389f2a8315167ede9e0b10 ] The PHY on BCM7278 has an additional bit that needs to be cleared: IDDQ_GLOBAL_PWR, without doing this, the PHY remains stuck in reset out of suspend/resume cycles. Fixes: 0fe9933804eb ("net: dsa: bcm_sf2: Add support for BCM7278 integrated switch") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/dsa/bcm_sf2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/net/dsa/bcm_sf2.c +++ b/drivers/net/dsa/bcm_sf2.c @@ -167,7 +167,7 @@ static void bcm_sf2_gphy_enable_set(stru reg = reg_readl(priv, REG_SPHY_CNTRL); if (enable) { reg |= PHY_RESET; - reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); + reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS); reg_writel(priv, reg, REG_SPHY_CNTRL); udelay(21); reg = reg_readl(priv, REG_SPHY_CNTRL); Patches currently in stable-queue which might be from f.fainelli@gmail.com are queue-4.14/phylink-ensure-the-phy-interface-mode-is-appropriately-set.patch queue-4.14/net-dsa-bcm_sf2-clear-iddq_global_pwr-bit-for-phy.patch queue-4.14/phylink-ensure-an-is-enabled.patch