* [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3
[not found] <1517022752-3053-1-git-send-email-chenhc@lemote.com>
@ 2018-01-27 3:19 ` Huacai Chen
2018-02-19 22:19 ` James Hogan
2018-01-27 3:20 ` [PATCH V2 05/12] MIPS: Loongson fix name confict - MEM_RESERVED Huacai Chen
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Huacai Chen @ 2018-01-27 3:19 UTC (permalink / raw)
To: Ralf Baechle
Cc: James Hogan, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen, # 3 . 15+
For multi-node Loongson-3 (NUMA configuration), r4k_blast_scache() can
only flush Node-0's scache. So we add r4k_blast_scache_node() by using
(CAC_BASE | (node_id << NODE_ADDRSPACE_SHIFT)) instead of CKSEG0 as the
start address.
Cc: <stable@vger.kernel.org> # 3.15+
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/r4kcache.h | 34 ++++++++++++++++++++++++++++++++
arch/mips/mm/c-r4k.c | 42 +++++++++++++++++++++++++++++++++-------
2 files changed, 69 insertions(+), 7 deletions(-)
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7f12d7e..c1f2806 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -747,4 +747,38 @@ __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
+#ifndef pa_to_nid
+#define pa_to_nid(addr) 0
+#endif
+
+#ifndef NODE_ADDRSPACE_SHIFT
+#define nid_to_addrbase(nid) 0
+#else
+#define nid_to_addrbase(nid) (nid << NODE_ADDRSPACE_SHIFT)
+#endif
+
+#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
+static inline void blast_##pfx##cache##lsize##_node(long node) \
+{ \
+ unsigned long start = CAC_BASE | nid_to_addrbase(node); \
+ unsigned long end = start + current_cpu_data.desc.waysize; \
+ unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
+ unsigned long ws_end = current_cpu_data.desc.ways << \
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
+ __##pfx##flush_prologue \
+ \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache##lsize##_unroll32(addr|ws, indexop); \
+ \
+ __##pfx##flush_epilogue \
+}
+
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
+__BUILD_BLAST_CACHE_NODE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+
#endif /* _ASM_R4KCACHE_H */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6f534b20..155f5f5 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -459,11 +459,28 @@ static void r4k_blast_scache_setup(void)
r4k_blast_scache = blast_scache128;
}
+static void (*r4k_blast_scache_node)(long node);
+
+static void r4k_blast_scache_node_setup(void)
+{
+ unsigned long sc_lsize = cpu_scache_line_size();
+
+ if (current_cpu_type() != CPU_LOONGSON3)
+ r4k_blast_scache_node = (void *)cache_noop;
+ else if (sc_lsize == 16)
+ r4k_blast_scache_node = blast_scache16_node;
+ else if (sc_lsize == 32)
+ r4k_blast_scache_node = blast_scache32_node;
+ else if (sc_lsize == 64)
+ r4k_blast_scache_node = blast_scache64_node;
+ else if (sc_lsize == 128)
+ r4k_blast_scache_node = blast_scache128_node;
+}
+
static inline void local_r4k___flush_cache_all(void * args)
{
switch (current_cpu_type()) {
case CPU_LOONGSON2:
- case CPU_LOONGSON3:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@@ -480,6 +497,10 @@ static inline void local_r4k___flush_cache_all(void * args)
r4k_blast_scache();
break;
+ case CPU_LOONGSON3:
+ r4k_blast_scache_node(get_ebase_cpunum() >> 2);
+ break;
+
case CPU_BMIPS5000:
r4k_blast_scache();
__sync();
@@ -839,9 +860,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
- if (size >= scache_size)
- r4k_blast_scache();
- else
+ if (size >= scache_size) {
+ if (current_cpu_type() != CPU_LOONGSON3)
+ r4k_blast_scache();
+ else
+ r4k_blast_scache_node(pa_to_nid(addr));
+ } else
blast_scache_range(addr, addr + size);
preempt_enable();
__sync();
@@ -872,9 +896,12 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
preempt_disable();
if (cpu_has_inclusive_pcaches) {
- if (size >= scache_size)
- r4k_blast_scache();
- else {
+ if (size >= scache_size) {
+ if (current_cpu_type() != CPU_LOONGSON3)
+ r4k_blast_scache();
+ else
+ r4k_blast_scache_node(pa_to_nid(addr));
+ } else {
/*
* There is no clearly documented alignment requirement
* for the cache instruction on MIPS processors and
@@ -1905,6 +1932,7 @@ void r4k_cache_init(void)
r4k_blast_scache_page_setup();
r4k_blast_scache_page_indexed_setup();
r4k_blast_scache_setup();
+ r4k_blast_scache_node_setup();
#ifdef CONFIG_EVA
r4k_blast_dcache_user_page_setup();
r4k_blast_icache_user_page_setup();
--
2.7.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V2 05/12] MIPS: Loongson fix name confict - MEM_RESERVED
[not found] <1517022752-3053-1-git-send-email-chenhc@lemote.com>
2018-01-27 3:19 ` [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
@ 2018-01-27 3:20 ` Huacai Chen
2018-01-27 3:21 ` [PATCH V2 06/12] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
[not found] ` <1517023381-17624-1-git-send-email-chenhc@lemote.com>
3 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2018-01-27 3:20 UTC (permalink / raw)
To: Ralf Baechle
Cc: James Hogan, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen, # 3 . 15+, YunQiang Su
MEM_RESERVED is used as a value of enum mem_type in include/linux/
edac.h. This will make failure to build for Loongson in some case:
for example with CONFIG_RAS enabled.
So here rename MEM_RESERVED to SYSTEM_RAM_RESERVED in Loongson code.
Cc: <stable@vger.kernel.org> # 3.15+
Reviewed-by: James Hogan <jhogan@kernel.org>
Signed-off-by: YunQiang Su <yunqiang.su@imgtec.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson64/boot_param.h | 2 +-
arch/mips/loongson64/common/mem.c | 2 +-
arch/mips/loongson64/loongson-3/numa.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index 4f69f08..8c286be 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -4,7 +4,7 @@
#define SYSTEM_RAM_LOW 1
#define SYSTEM_RAM_HIGH 2
-#define MEM_RESERVED 3
+#define SYSTEM_RAM_RESERVED 3
#define PCI_IO 4
#define PCI_MEM 5
#define LOONGSON_CFG_REG 6
diff --git a/arch/mips/loongson64/common/mem.c b/arch/mips/loongson64/common/mem.c
index b01d524..c549e52 100644
--- a/arch/mips/loongson64/common/mem.c
+++ b/arch/mips/loongson64/common/mem.c
@@ -79,7 +79,7 @@ void __init prom_init_memory(void)
(u64)loongson_memmap->map[i].mem_size << 20,
BOOT_MEM_RAM);
break;
- case MEM_RESERVED:
+ case SYSTEM_RAM_RESERVED:
add_memory_region(loongson_memmap->map[i].mem_start,
(u64)loongson_memmap->map[i].mem_size << 20,
BOOT_MEM_RESERVED);
diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/loongson-3/numa.c
index f17ef52..9717106 100644
--- a/arch/mips/loongson64/loongson-3/numa.c
+++ b/arch/mips/loongson64/loongson-3/numa.c
@@ -166,7 +166,7 @@ static void __init szmem(unsigned int node)
memblock_add_node(PFN_PHYS(start_pfn),
PFN_PHYS(end_pfn - start_pfn), node);
break;
- case MEM_RESERVED:
+ case SYSTEM_RAM_RESERVED:
pr_info("Node%d: mem_type:%d, mem_start:0x%llx, mem_size:0x%llx MB\n",
(u32)node_id, mem_type, mem_start, mem_size);
add_memory_region((node_id << 44) + mem_start,
--
2.7.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V2 06/12] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent()
[not found] <1517022752-3053-1-git-send-email-chenhc@lemote.com>
2018-01-27 3:19 ` [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-01-27 3:20 ` [PATCH V2 05/12] MIPS: Loongson fix name confict - MEM_RESERVED Huacai Chen
@ 2018-01-27 3:21 ` Huacai Chen
[not found] ` <1517023381-17624-1-git-send-email-chenhc@lemote.com>
3 siblings, 0 replies; 6+ messages in thread
From: Huacai Chen @ 2018-01-27 3:21 UTC (permalink / raw)
To: Ralf Baechle
Cc: James Hogan, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen, # 3 . 8+
This patch is borrowed from ARM64 to ensure pmd_present() returns false
after pmd_mknotpresent(). This is needed for THP.
Cc: <stable@vger.kernel.org> # 3.8+
References: 5bb1cc0ff9a6 ("arm64: Ensure pmd_present() returns false after pmd_mknotpresent()")
Reviewed-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/pgtable-64.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 0036ea0..93a9dce 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -265,6 +265,11 @@ static inline int pmd_bad(pmd_t pmd)
static inline int pmd_present(pmd_t pmd)
{
+#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+ if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
+ return pmd_val(pmd) & _PAGE_PRESENT;
+#endif
+
return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}
--
2.7.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V2 11/12] MIPS: Loongson-3: Fix CPU UART irq delivery problem
[not found] ` <1517023381-17624-1-git-send-email-chenhc@lemote.com>
@ 2018-01-27 3:23 ` Huacai Chen
2018-02-20 21:49 ` James Hogan
0 siblings, 1 reply; 6+ messages in thread
From: Huacai Chen @ 2018-01-27 3:23 UTC (permalink / raw)
To: Ralf Baechle
Cc: James Hogan, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Huacai Chen, stable
Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
other CPUs) may cause interrupts be lost, especially in multi-package
machines (Package-0's UART irq cannot be delivered to others). So make
mask_loongson_irq() and unmask_loongson_irq() be no-ops.
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/loongson64/loongson-3/irq.c | 41 ++---------------------------------
1 file changed, 2 insertions(+), 39 deletions(-)
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
index cbeb20f..e8381ec 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -102,45 +102,8 @@ static struct irqaction cascade_irqaction = {
.name = "cascade",
};
-static inline void mask_loongson_irq(struct irq_data *d)
-{
- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
- irq_disable_hazard();
-
- /* Workaround: UART IRQ may deliver to any core */
- if (d->irq == LOONGSON_UART_IRQ) {
- int cpu = smp_processor_id();
- int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
- int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
- u64 intenclr_addr = smp_group[node_id] |
- (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
- u64 introuter_lpc_addr = smp_group[node_id] |
- (u64)(&LOONGSON_INT_ROUTER_LPC);
-
- *(volatile u32 *)intenclr_addr = 1 << 10;
- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
- }
-}
-
-static inline void unmask_loongson_irq(struct irq_data *d)
-{
- /* Workaround: UART IRQ may deliver to any core */
- if (d->irq == LOONGSON_UART_IRQ) {
- int cpu = smp_processor_id();
- int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
- int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
- u64 intenset_addr = smp_group[node_id] |
- (u64)(&LOONGSON_INT_ROUTER_INTENSET);
- u64 introuter_lpc_addr = smp_group[node_id] |
- (u64)(&LOONGSON_INT_ROUTER_LPC);
-
- *(volatile u32 *)intenset_addr = 1 << 10;
- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
- }
-
- set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
- irq_enable_hazard();
-}
+static inline void mask_loongson_irq(struct irq_data *d) { }
+static inline void unmask_loongson_irq(struct irq_data *d) { }
/* For MIPS IRQs which shared by all cores */
static struct irq_chip loongson_irq_chip = {
--
2.7.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3
2018-01-27 3:19 ` [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
@ 2018-02-19 22:19 ` James Hogan
0 siblings, 0 replies; 6+ messages in thread
From: James Hogan @ 2018-02-19 22:19 UTC (permalink / raw)
To: Huacai Chen
Cc: Ralf Baechle, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, # 3 . 15+
[-- Attachment #1: Type: text/plain, Size: 3534 bytes --]
On Sat, Jan 27, 2018 at 11:19:05AM +0800, Huacai Chen wrote:
> For multi-node Loongson-3 (NUMA configuration), r4k_blast_scache() can
> only flush Node-0's scache. So we add r4k_blast_scache_node() by using
> (CAC_BASE | (node_id << NODE_ADDRSPACE_SHIFT)) instead of CKSEG0 as the
> start address.
>
> Cc: <stable@vger.kernel.org> # 3.15+
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> ---
> arch/mips/include/asm/r4kcache.h | 34 ++++++++++++++++++++++++++++++++
> arch/mips/mm/c-r4k.c | 42 +++++++++++++++++++++++++++++++++-------
> 2 files changed, 69 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
> index 7f12d7e..c1f2806 100644
> --- a/arch/mips/include/asm/r4kcache.h
> +++ b/arch/mips/include/asm/r4kcache.h
> @@ -747,4 +747,38 @@ __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
> __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
> __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
>
> +#ifndef pa_to_nid
> +#define pa_to_nid(addr) 0
> +#endif
> +
> +#ifndef NODE_ADDRSPACE_SHIFT
To be sure you get the right definition of both of these if they exist,
and wherever this header is included, we should explicitly #include the
appropriate header (asm/mmzone.h?) from this header.
> +#define nid_to_addrbase(nid) 0
> +#else
> +#define nid_to_addrbase(nid) (nid << NODE_ADDRSPACE_SHIFT)
Technically this should have parentheses around nid.
It seems slightly inconsistent to have pa_to_nid() defined in mmzone.h,
but not the reverse nid_to_addrbase(). NODE_ADDRSPACE_SHIFT is very
loongson specific afterall.
Would it make sense to move it into
arch/mips/include/asm/mach-loongson64/mmzone.h and put the 0 definition
in #ifndef nid_to_addrbase?
> +#endif
> +
> +#define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
I think this is worthy of a quick comment to explain that this is very
specific to Loongson3.
> #endif /* _ASM_R4KCACHE_H */
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 6f534b20..155f5f5 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
...
> @@ -480,6 +497,10 @@ static inline void local_r4k___flush_cache_all(void * args)
> r4k_blast_scache();
> break;
>
> + case CPU_LOONGSON3:
> + r4k_blast_scache_node(get_ebase_cpunum() >> 2);
I assume this can't use cpu_to_node() because it needs to work even when
NUMA=n? If so, I think it deserves a brief comment to explain that.
> + break;
> +
> case CPU_BMIPS5000:
> r4k_blast_scache();
> __sync();
> @@ -839,9 +860,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
>
> preempt_disable();
> if (cpu_has_inclusive_pcaches) {
> - if (size >= scache_size)
> - r4k_blast_scache();
> - else
> + if (size >= scache_size) {
> + if (current_cpu_type() != CPU_LOONGSON3)
> + r4k_blast_scache();
> + else
> + r4k_blast_scache_node(pa_to_nid(addr));
If I read this right, addr is a virtual address so this feels a bit
hacky, but I suppose its harmless since it'll probably always be memory
in xkphys space where pa_to_nid() will do the right thing. Perhaps a
comment along the lines of:
/* This assumes that addr is in XKPhys */
> + } else
Please keep braces consistent, i.e. add to the trailing else statement
too.
Other than those niggles, the actual mechanism looks reasonable to me.
Thanks
James
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2 11/12] MIPS: Loongson-3: Fix CPU UART irq delivery problem
2018-01-27 3:23 ` [PATCH V2 11/12] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
@ 2018-02-20 21:49 ` James Hogan
0 siblings, 0 replies; 6+ messages in thread
From: James Hogan @ 2018-02-20 21:49 UTC (permalink / raw)
To: Huacai Chen
Cc: Ralf Baechle, Steven J . Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, stable
[-- Attachment #1: Type: text/plain, Size: 842 bytes --]
On Sat, Jan 27, 2018 at 11:23:00AM +0800, Huacai Chen wrote:
> Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
> other CPUs) may cause interrupts be lost, especially in multi-package
> machines (Package-0's UART irq cannot be delivered to others). So make
> mask_loongson_irq() and unmask_loongson_irq() be no-ops.
>
> Cc: stable@vger.kernel.org
...
> -static inline void mask_loongson_irq(struct irq_data *d)
> -{
> - clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
> - irq_disable_hazard();
> -
> - /* Workaround: UART IRQ may deliver to any core */
Wouldn't removing this self-described "workaround" bring back the
original problem?
At the very least you need a much better explanation of why these
workarounds are no longer applicable and can be safely removed.
Cheers
James
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2018-01-27 3:19 ` [PATCH V2 04/12] MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 Huacai Chen
2018-02-19 22:19 ` James Hogan
2018-01-27 3:20 ` [PATCH V2 05/12] MIPS: Loongson fix name confict - MEM_RESERVED Huacai Chen
2018-01-27 3:21 ` [PATCH V2 06/12] MIPS: Ensure pmd_present() returns false after pmd_mknotpresent() Huacai Chen
[not found] ` <1517023381-17624-1-git-send-email-chenhc@lemote.com>
2018-01-27 3:23 ` [PATCH V2 11/12] MIPS: Loongson-3: Fix CPU UART irq delivery problem Huacai Chen
2018-02-20 21:49 ` James Hogan
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