From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:58048 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751492AbeBWLAW (ORCPT ); Fri, 23 Feb 2018 06:00:22 -0500 Subject: Patch "pinctrl: sunxi: Fix A64 UART mux value" has been added to the 4.9-stable tree To: andre.przywara@arm.com, alexander.levin@microsoft.com, gregkh@linuxfoundation.org, linus.walleij@linaro.org, wens@csie.org Cc: , From: Date: Fri, 23 Feb 2018 11:59:14 +0100 Message-ID: <15193835547230@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled pinctrl: sunxi: Fix A64 UART mux value to the 4.9-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pinctrl-sunxi-fix-a64-uart-mux-value.patch and it can be found in the queue-4.9 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From foo@baz Fri Feb 23 11:48:40 CET 2018 From: Andre Przywara Date: Sat, 25 Nov 2017 12:12:30 +0000 Subject: pinctrl: sunxi: Fix A64 UART mux value From: Andre Przywara [ Upstream commit 7c5c2c2d18d778e51fd8b899965097168306031c ] To use pin PF4 as the RX signal of UART0, we have to write 0b011 into the respective pin controller register. Fix the wrong value we had in our table so far. Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Signed-off-by: Andre Przywara Acked-by: Chen-Yu Tsai Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c @@ -428,7 +428,7 @@ static const struct sunxi_desc_pin a64_p SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ + SUNXI_FUNCTION(0x3, "uart0")), /* RX */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), Patches currently in stable-queue which might be from andre.przywara@arm.com are queue-4.9/pinctrl-sunxi-fix-a64-uart-mux-value.patch queue-4.9/pinctrl-sunxi-fix-a80-interrupt-pin-bank.patch