Re: [PATCH AUTOSEL for 4.15 36/78] net: phy: meson-gxl: check phy_write return value

[Jerome Brunet <jbrunet@baylibre.com>]

On Thu, 2018-03-08 at 04:56 +0000, Sasha Levin wrote:
> From: Jerome Brunet <jbrunet@baylibre.com>
> 
> [ Upstream commit 9042b46eda33ef5db3cdfc9e12b3c8cabb196141 ]
> 
> Always check phy_write return values. Better to be safe than sorry
> 
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> Signed-off-by: David S. Miller <davem@davemloft.net>
> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>

Hi Sasha,

I have recently received a few mails from you with [PATCH AUTOSEL], such as this
one. I'm wondering what are the criteria to select these patches? This one does
not have a "Fixes" tag and, I believe, stable was not CCed of the original
patch. Do you have another selection method ?

I really sorry if you already got this question a thousand times.

I have nothing against this patch making its way to a stable release BTW, it
won't do any harm.

> ---
>  drivers/net/phy/meson-gxl.c | 50 ++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 38 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
> index 842eb871a6e3..f431c83ba0b5 100644
> --- a/drivers/net/phy/meson-gxl.c
> +++ b/drivers/net/phy/meson-gxl.c
> @@ -26,27 +26,53 @@
>  
>  static int meson_gxl_config_init(struct phy_device *phydev)
>  {
> +	int ret;
> +
>  	/* Enable Analog and DSP register Bank access by */
> -	phy_write(phydev, 0x14, 0x0000);
> -	phy_write(phydev, 0x14, 0x0400);
> -	phy_write(phydev, 0x14, 0x0000);
> -	phy_write(phydev, 0x14, 0x0400);
> +	ret = phy_write(phydev, 0x14, 0x0000);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x0400);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x0000);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x0400);
> +	if (ret)
> +		return ret;
>  
>  	/* Write Analog register 23 */
> -	phy_write(phydev, 0x17, 0x8E0D);
> -	phy_write(phydev, 0x14, 0x4417);
> +	ret = phy_write(phydev, 0x17, 0x8E0D);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x4417);
> +	if (ret)
> +		return ret;
>  
>  	/* Enable fractional PLL */
> -	phy_write(phydev, 0x17, 0x0005);
> -	phy_write(phydev, 0x14, 0x5C1B);
> +	ret = phy_write(phydev, 0x17, 0x0005);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x5C1B);
> +	if (ret)
> +		return ret;
>  
>  	/* Program fraction FR_PLL_DIV1 */
> -	phy_write(phydev, 0x17, 0x029A);
> -	phy_write(phydev, 0x14, 0x5C1D);
> +	ret = phy_write(phydev, 0x17, 0x029A);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x5C1D);
> +	if (ret)
> +		return ret;
>  
>  	/* Program fraction FR_PLL_DIV1 */
> -	phy_write(phydev, 0x17, 0xAAAA);
> -	phy_write(phydev, 0x14, 0x5C1C);
> +	ret = phy_write(phydev, 0x17, 0xAAAA);
> +	if (ret)
> +		return ret;
> +	ret = phy_write(phydev, 0x14, 0x5C1C);
> +	if (ret)
> +		return ret;
>  
>  	return 0;
>  }