From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linuxfoundation.org ([140.211.169.12]:41486 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754383AbeCRQAg (ORCPT ); Sun, 18 Mar 2018 12:00:36 -0400 Subject: Patch "clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor" has been added to the 4.9-stable tree To: wens@csie.org, alexander.levin@microsoft.com, gregkh@linuxfoundation.org, maxime.ripard@free-electrons.com Cc: , From: Date: Sun, 18 Mar 2018 16:59:55 +0100 Message-ID: <1521388795142136@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: This is a note to let you know that I've just added the patch titled clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor to the 4.9-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-sunxi-ng-a33-add-offset-and-minimum-value-for-ddr1-pll-n-factor.patch and it can be found in the queue-4.9 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let know about it. >>From foo@baz Sun Mar 18 16:55:33 CET 2018 From: Chen-Yu Tsai Date: Wed, 5 Apr 2017 14:37:44 +0800 Subject: clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor From: Chen-Yu Tsai [ Upstream commit 68f37d862403e8f95337b2eca90af15d0b8cd5d7 ] The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks. It is a clock multiplier, with the effective multiplier in the range of 12 ~ 255 and no offset between the multiplier value and the value programmed into the register. Implement the zero offset and minimum value of 12 for this clock. Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK( BIT(28), /* lock */ CLK_SET_RATE_UNGATE); -/* TODO: Fix N */ -static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", - "osc24M", 0x04c, - 8, 6, /* N */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static struct ccu_mult pll_ddr1_clk = { + .enable = BIT(31), + .lock = BIT(28), + .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0), + .common = { + .reg = 0x04c, + .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M", + &ccu_mult_ops, + CLK_SET_RATE_UNGATE), + }, +}; static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; Patches currently in stable-queue which might be from wens@csie.org are queue-4.9/drm-sun4i-fix-up-error-path-cleanup-for-master-bind-function.patch queue-4.9/drm-sun4i-set-drm_crtc.port-to-the-underlying-tcon-s-output-port-node.patch queue-4.9/drm-sun4i-fix-tcon-clock-and-regmap-initialization-sequence.patch queue-4.9/clk-sunxi-ng-a33-add-offset-and-minimum-value-for-ddr1-pll-n-factor.patch