From: <gregkh@linuxfoundation.org>
To: jernej.skrabec@siol.net, alexander.levin@microsoft.com,
gregkh@linuxfoundation.org, wens@csie.org
Cc: <stable@vger.kernel.org>, <stable-commits@vger.kernel.org>
Subject: Patch "clk: sunxi-ng: a83t: Add M divider to TCON1 clock" has been added to the 4.15-stable tree
Date: Mon, 09 Apr 2018 11:36:11 +0200 [thread overview]
Message-ID: <1523266571103168@kroah.com> (raw)
This is a note to let you know that I've just added the patch titled
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-sunxi-ng-a83t-add-m-divider-to-tcon1-clock.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Mon Apr 9 10:16:32 CEST 2018
From: "Jernej Škrabec" <jernej.skrabec@siol.net>
Date: Sat, 30 Dec 2017 22:01:54 +0100
Subject: clk: sunxi-ng: a83t: Add M divider to TCON1 clock
From: "Jernej Škrabec" <jernej.skrabec@siol.net>
[ Upstream commit 7dbc7f5f4904cfddc199af171ea095490a434f15 ]
TCON1 also has M divider, contrary to TCON0. And the mux is only
2 bits wide, instead of 3.
Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[wens@csie.org: Add description about mux width difference]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -493,8 +493,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk
0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static const char * const tcon1_parents[] = { "pll-video1" };
-static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,
- 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
+ 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
Patches currently in stable-queue which might be from jernej.skrabec@siol.net are
queue-4.15/clk-sunxi-ng-a83t-add-m-divider-to-tcon1-clock.patch
reply other threads:[~2018-04-09 9:36 UTC|newest]
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