* [PATCH] ARM: dts: socfpga: Fix SDRAM node address for Arria10
@ 2018-09-25 15:21 thor.thayer
2018-10-26 20:14 ` Thor Thayer
0 siblings, 1 reply; 3+ messages in thread
From: thor.thayer @ 2018-09-25 15:21 UTC (permalink / raw)
To: dinguyen, robh+dt, mark.rutland
Cc: catalin.marinas, will.deacon, devicetree, linux-arm-kernel,
Thor Thayer, stable
From: Thor Thayer <thor.thayer@linux.intel.com>
The address in the SDRAM node was incorrect. Fix this to agree with the
correct address and to match the reg definition block.
Cc: stable@vger.kernel.org
Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support")
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 791ca15c799e..bd1985694bca 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -601,7 +601,7 @@
status = "disabled";
};
- sdr: sdr@ffc25000 {
+ sdr: sdr@ffcfb100 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffcfb100 0x80>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] ARM: dts: socfpga: Fix SDRAM node address for Arria10
2018-09-25 15:21 [PATCH] ARM: dts: socfpga: Fix SDRAM node address for Arria10 thor.thayer
@ 2018-10-26 20:14 ` Thor Thayer
2018-10-26 20:52 ` Dinh Nguyen
0 siblings, 1 reply; 3+ messages in thread
From: Thor Thayer @ 2018-10-26 20:14 UTC (permalink / raw)
To: dinguyen, robh+dt, mark.rutland
Cc: catalin.marinas, will.deacon, devicetree, linux-arm-kernel,
stable
Gentle ping.
On 9/25/18 10:21 AM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> The address in the SDRAM node was incorrect. Fix this to agree with the
> correct address and to match the reg definition block.
>
> Cc: stable@vger.kernel.org
> Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support")
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 791ca15c799e..bd1985694bca 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -601,7 +601,7 @@
> status = "disabled";
> };
>
> - sdr: sdr@ffc25000 {
> + sdr: sdr@ffcfb100 {
> compatible = "altr,sdr-ctl", "syscon";
> reg = <0xffcfb100 0x80>;
> };
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] ARM: dts: socfpga: Fix SDRAM node address for Arria10
2018-10-26 20:14 ` Thor Thayer
@ 2018-10-26 20:52 ` Dinh Nguyen
0 siblings, 0 replies; 3+ messages in thread
From: Dinh Nguyen @ 2018-10-26 20:52 UTC (permalink / raw)
To: thor.thayer, robh+dt, mark.rutland
Cc: catalin.marinas, will.deacon, devicetree, linux-arm-kernel,
stable
On 10/26/2018 03:14 PM, Thor Thayer wrote:
> Gentle ping.
>
> On 9/25/18 10:21 AM, thor.thayer@linux.intel.com wrote:
>> From: Thor Thayer <thor.thayer@linux.intel.com>
>>
>> The address in the SDRAM node was incorrect. Fix this to agree with the
>> correct address and to match the reg definition block.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS
>> support")
>> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
>> ---
>> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
This is already in arm-soc/next/dt and should land in v4.20-rc1.
Dinh
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-10-27 5:30 UTC | newest]
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2018-09-25 15:21 [PATCH] ARM: dts: socfpga: Fix SDRAM node address for Arria10 thor.thayer
2018-10-26 20:14 ` Thor Thayer
2018-10-26 20:52 ` Dinh Nguyen
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