From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB9C0C282CE for ; Fri, 12 Apr 2019 02:42:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA9C621721 for ; Fri, 12 Apr 2019 02:42:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726685AbfDLCma (ORCPT ); Thu, 11 Apr 2019 22:42:30 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:56692 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726661AbfDLCma (ORCPT ); Thu, 11 Apr 2019 22:42:30 -0400 X-UUID: 66d88c511ae54b0db42b8d4c3e9155bc-20190412 X-UUID: 66d88c511ae54b0db42b8d4c3e9155bc-20190412 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1157262839; Fri, 12 Apr 2019 10:42:22 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 12 Apr 2019 10:42:17 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 12 Apr 2019 10:42:17 +0800 Message-ID: <1555036937.2654.5.camel@mtksdaap41> Subject: Re: [PATCH v5 6/9] clk: mediatek: Add flags support for mtk_gate data From: Weiyi Lu To: Stephen Boyd CC: Matthias Brugger , Nicolas Boichat , Rob Herring , Stephen Boyd , James Liao , , , , Fan Chen , , , Date: Fri, 12 Apr 2019 10:42:17 +0800 In-Reply-To: <155501399858.20095.16525048679717411283@swboyd.mtv.corp.google.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> <20190305050546.23431-8-weiyi.lu@mediatek.com> <155501399858.20095.16525048679717411283@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, 2019-04-11 at 13:19 -0700, Stephen Boyd wrote: > Quoting Weiyi Lu (2019-03-04 21:05:43) > > On some Mediatek platforms, there are critical clocks of > > clock gate type. > > To register clock gate with flags CLK_IS_CRITICAL, > > we need to add the flags field in mtk_gate data and register APIs. > > > > Signed-off-by: Weiyi Lu > > This patch doesn't apply, because it's already there via commit > 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate"). > Got it, but just catch a minor defect by 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate"). init.flags = CLK_SET_RATE_PARENT; ... init.flags = flags; I'll send a fix later. Thanks for the help on the MT8183 clk series. > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek