From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB80CA9EBD for ; Sun, 27 Oct 2019 13:54:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C54A1214AF for ; Sun, 27 Oct 2019 13:54:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572184496; bh=HRi+5w6MOLc3uve+8b7Zxt8WYaKElChqKvvgXti+tik=; h=Subject:To:Cc:From:Date:List-ID:From; b=FbiR4g/dgn0IRsVQEC783BR1Cde/5QbER4VYONEfSWxQ4muRhnUEbEiaMX7xVQfrg BhQdFJAX8nvIJ1cV6f5tkgxw17MwJh1cJ26MjG2JRAntCYmVifGpBPiahvdCxAo/IU MNtA67dGxH4aVgSxyviX+r7cXvkQ5D8VQWCEDvoI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726736AbfJ0Ny4 (ORCPT ); Sun, 27 Oct 2019 09:54:56 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:60463 "EHLO out3-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726750AbfJ0Ny4 (ORCPT ); Sun, 27 Oct 2019 09:54:56 -0400 Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 7C21121C4E; Sun, 27 Oct 2019 09:54:55 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute6.internal (MEProxy); Sun, 27 Oct 2019 09:54:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:message-id:mime-version:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=Kh/stX BqeBQOtVQtTu9KVRb5BnjVYfdlr4msICyjM0Y=; b=NFvx8qK3ieSdD0ITWlEWj2 ZU/PD11+u+5wDA5i9LEUpFnj5gruH+IzcNN6XHYaML2N1n24MoZfCgYuJEXxWTki iS3CgQPYVhRElhn+R+mrJ8L2Dyp2itCLlCrdcJYdZGTop1bZ9xmEQEdNnZDS401A GrXBxqhhP/hCw/m/aVm/L6iIcABlUqP8tAXDUu6gz2nBp9naZ4z7/muszUPD/SUA BMbEQO4dg5FbaFxZOqBenXJf1BaxQK+4wRKZ2varj1z+ttNIj3nCYDSLn1h6Z6Kb PqFJmNq7jYQEbyuADEIjTflT07IcH45egsYMlGMhABNPM2ohiyEx+NeuIE3Ig1xQ == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrleejgdeitdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhepuffvhfffkfggtgfgsehtkeertddttd flnecuhfhrohhmpeeoghhrvghgkhhhsehlihhnuhigfhhouhhnuggrthhiohhnrdhorhhg qeenucfkphepjeejrddvgedurddvvdelrddvfedvnecurfgrrhgrmhepmhgrihhlfhhroh hmpehgrhgvgheskhhrohgrhhdrtghomhenucevlhhushhtvghrufhiiigvpeel X-ME-Proxy: Received: from localhost (unknown [77.241.229.232]) by mail.messagingengine.com (Postfix) with ESMTPA id 267D1D6005E; Sun, 27 Oct 2019 09:54:55 -0400 (EDT) Subject: FAILED: patch "[PATCH] arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected" failed to apply to 4.4-stable tree To: maz@kernel.org, marc.zyngier@arm.com, stable@vger.kernel.org, will@kernel.org Cc: From: Date: Sun, 27 Oct 2019 14:54:44 +0100 Message-ID: <157218448440196@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The patch below does not apply to the 4.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 603afdc9438ac546181e843f807253d75d3dbc45 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Fri, 13 Sep 2019 10:57:50 +0100 Subject: [PATCH] arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected Allow the user to select the workaround for TX2-219, and update the silicon-errata.rst file to reflect this. Cc: Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 17ea3fecddaa..ab7ed2fd072f 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -107,6 +107,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX2 SMMUv3| #126 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 41a9b4257b72..7d36fd95ae5a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -617,6 +617,23 @@ config CAVIUM_ERRATUM_30115 If unsure, say Y. +config CAVIUM_TX2_ERRATUM_219 + bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" + default y + help + On Cavium ThunderX2, a load, store or prefetch instruction between a + TTBR update and the corresponding context synchronizing operation can + cause a spurious Data Abort to be delivered to any hardware thread in + the CPU core. + + Work around the issue by avoiding the problematic code sequence and + trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The + trap handler performs the corresponding register access, skips the + instruction and ensures context synchronization by virtue of the + exception return. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y