From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 448F6C3A5A0 for ; Mon, 20 Apr 2020 12:09:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2516B221F4 for ; Mon, 20 Apr 2020 12:09:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587384555; bh=wmPpzr16MkLptqjgs3cCXdOarCbrTBS9JEVRvACC9V4=; h=Subject:To:From:Date:List-ID:From; b=1SQOYvVX454rzuGfjveu3qN9mPGdBw015LN2pPZw3KecCXeGVWyDGNGzhxL8qdmYm uhuRbDW7TE+Zjy5yJpq3waUQBTsrcIdAPZilQWqgHbgMp8KTolxxHfXqrd17nZK3RF 6P/Yzjvxg/UgyRL8s8/9N6UB6vPjq/Hm1gmAc2ME= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726020AbgDTMJO (ORCPT ); Mon, 20 Apr 2020 08:09:14 -0400 Received: from mail.kernel.org ([198.145.29.99]:47544 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725886AbgDTMJO (ORCPT ); Mon, 20 Apr 2020 08:09:14 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 22D2B206D6; Mon, 20 Apr 2020 12:09:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1587384553; bh=wmPpzr16MkLptqjgs3cCXdOarCbrTBS9JEVRvACC9V4=; h=Subject:To:From:Date:From; b=wjpK7T/h6ZwyadgSo5qtmO+7MSkOp9W8UczAyYyLNmRLHnuR6TUlu9AIG1r6rATeO aYWETs60iL4N/wD7e8rCX+sYK5F0pmJtm6cMGHUjGK6qYf5xHe0m7jmRVX9xLPToLA e2nm9hGqTGwLuKvvudqnGdFdQiJhntXtrZHFAny0= Subject: patch "iio: xilinx-xadc: Fix sequencer configuration for aux channels in" added to staging-linus To: lars@metafoo.de, Jonathan.Cameron@huawei.com, Stable@vger.kernel.org From: Date: Mon, 20 Apr 2020 14:08:48 +0200 Message-ID: <158738452810168@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org This is a note to let you know that I've just added the patch titled iio: xilinx-xadc: Fix sequencer configuration for aux channels in to my staging git tree which can be found at git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git in the staging-linus branch. The patch will show up in the next release of the linux-next tree (usually sometime within the next 24 hours during the week.) The patch will hopefully also be merged in Linus's tree for the next -rc kernel release. If you have any questions about this process, please let me know. >From 8bef455c8b1694547ee59e8b1939205ed9d901a6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 3 Apr 2020 15:27:15 +0200 Subject: iio: xilinx-xadc: Fix sequencer configuration for aux channels in simultaneous mode The XADC has two internal ADCs. Depending on the mode it is operating in either one or both of them are used. The device manual calls this continuous (one ADC) and simultaneous (both ADCs) mode. The meaning of the sequencing register for the aux channels changes depending on the mode. In continuous mode each bit corresponds to one of the 16 aux channels. And the single ADC will convert them one by one in order. In simultaneous mode the aux channels are split into two groups the first 8 channels are assigned to the first ADC and the other 8 channels to the second ADC. The upper 8 bits of the sequencing register are unused and the lower 8 bits control both ADCs. This means a bit needs to be set if either the corresponding channel from the first group or the second group (or both) are set. Currently the driver does not have the special handling required for simultaneous mode. Add it. Signed-off-by: Lars-Peter Clausen Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: Signed-off-by: Jonathan Cameron --- drivers/iio/adc/xilinx-xadc-core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 62ded9683a57..1aeaeafce589 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -798,6 +798,16 @@ static int xadc_preenable(struct iio_dev *indio_dev) if (ret) goto err; + /* + * In simultaneous mode the upper and lower aux channels are samples at + * the same time. In this mode the upper 8 bits in the sequencer + * register are don't care and the lower 8 bits control two channels + * each. As such we must set the bit if either the channel in the lower + * group or the upper group is enabled. + */ + if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS) + scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000; + ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16); if (ret) goto err; -- 2.26.1