From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84ABCC433F5 for ; Mon, 24 Jan 2022 12:43:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239284AbiAXMnp (ORCPT ); Mon, 24 Jan 2022 07:43:45 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:49696 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239181AbiAXMno (ORCPT ); Mon, 24 Jan 2022 07:43:44 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A2182B80EFA for ; Mon, 24 Jan 2022 12:43:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB7E1C340E4; Mon, 24 Jan 2022 12:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1643028222; bh=kVMEqBN2zfhn7DnExmEAifbXJt2SnZxrDIjKuPRz3Wg=; h=Subject:To:Cc:From:Date:From; b=LiktMPGjix/FzepNnafAAX13VrnSabNFOTPSGJuUbM+GZ7jXA7tYwBAqLAMImPl8V kyRgLImyAGhPa/JS4oS4S8KIizK8M5+EP1KeHIJKFOJ6J2c7ZrWTgbzPW87rL/Oq/Y 81eZjkkJbbG/YID1EntWntF8j/UVFO89UbtZvzbA= Subject: FAILED: patch "[PATCH] net: axienet: Wait for PhyRstCmplt after core reset" failed to apply to 5.4-stable tree To: robert.hancock@calian.com, andrew@lunn.ch, davem@davemloft.net Cc: From: Date: Mon, 24 Jan 2022 13:43:39 +0100 Message-ID: <164302821910435@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ANSI_X3.4-1968 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The patch below does not apply to the 5.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From b400c2f4f4c53c86594dd57098970d97d488bfde Mon Sep 17 00:00:00 2001 From: Robert Hancock Date: Tue, 18 Jan 2022 15:41:25 -0600 Subject: [PATCH] net: axienet: Wait for PhyRstCmplt after core reset When resetting the device, wait for the PhyRstCmplt bit to be set in the interrupt status register before continuing initialization, to ensure that the core is actually ready. When using an external PHY, this also ensures we do not start trying to access the PHY while it is still in reset. The PHY reset is initiated by the core reset which is triggered just above, but remains asserted for 5ms after the core is reset according to the documentation. The MgtRdy bit could also be waited for, but unfortunately when using 7-series devices, the bit does not appear to work as documented (it seems to behave as some sort of link state indication and not just an indication the transceiver is ready) so it can't really be relied on for this purpose. Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet driver") Signed-off-by: Robert Hancock Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 9c5b24af61fa..3a2d7e8c3f66 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_local *lp) return ret; } + /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */ + ret = read_poll_timeout(axienet_ior, value, + value & XAE_INT_PHYRSTCMPLT_MASK, + DELAY_OF_ONE_MILLISEC, 50000, false, lp, + XAE_IS_OFFSET); + if (ret) { + dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", __func__); + return ret; + } + return 0; }