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[115.64.212.59]) by smtp.gmail.com with ESMTPSA id q1sm2911458pfs.112.2022.02.24.03.13.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 03:13:30 -0800 (PST) Date: Thu, 24 Feb 2022 21:13:25 +1000 From: Nicholas Piggin Subject: Re: [PATCH 2/3] powerpc: fix build errors To: Arnd Bergmann Cc: Anders Roxell , Linux Kernel Mailing List , linuxppc-dev , Michael Ellerman , "# 3.4.x" References: <20220223135820.2252470-1-anders.roxell@linaro.org> <20220223135820.2252470-2-anders.roxell@linaro.org> <1645670923.t0z533n7uu.astroid@bobo.none> <1645678884.dsm10mudmp.astroid@bobo.none> <1645694174.z03tip9set.astroid@bobo.none> In-Reply-To: MIME-Version: 1.0 Message-Id: <1645700767.qxyu8a9wl9.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Excerpts from Arnd Bergmann's message of February 24, 2022 8:20 pm: > On Thu, Feb 24, 2022 at 11:11 AM Nicholas Piggin wrot= e: >> Excerpts from Arnd Bergmann's message of February 24, 2022 6:55 pm: >> > On Thu, Feb 24, 2022 at 6:05 AM Nicholas Piggin wr= ote: >> > We had the same thing on Arm a few years ago when binutils >> > started enforcing this more strictly, and it does catch actual >> > bugs. I think annotating individual inline asm statements is >> > the best choice here, as that documents what the intention is. >> >> A few cases where there are differences in privileged instructions >> (that won't be compiler generated), that will be done anyway. >> >> For new instructions added to the ISA though? I think it's ugly and >> unecesaary. There is no ambiguity about the intention when you see >> a lharx instruction is there? >> >> It would delinate instructions that can't be used on all processors >> but I don't see much advantage there, it's not an exhaustive check >> because we have other restrictions on instructions in the kernel >> environment. And why would inline asm be special but not the rest >> of the asm? Would you propose to put these .machine directives >> everywhere in thousands of lines of asm code in the kernel? I >> don't know that it's an improvement. And inline asm is a small >> fraction of instructions. >=20 > Most of the code is fine, as we tend to only build .S files that > are for the given target CPU, That's not true on powerpc at least. grep FTR_SECTION. Not all of them are different ISA, but it's more than just the CPU_FTR_ARCH ones which only started about POWER7. > the explicit .machine directives are > only needed when you have a file that mixes instructions for > incompatible machines, using a runtime detection. Right. There are .S files are in that category. And a lot of it for inline and .S we probably skirt entirely due to using raw=20 instruction encoding because of old toolchains (which gets no error=20 checking at all) which we really should tidy up and trim. >=20 >> Right that should be caught if you just pass -m architecture >> to the assembler that does not include the mtpmr. 32-bit is a lot more >> complicated than 64s like this though, so it's pssible in some cases >> you will want more checking and -m + some .machine directives >> will work better. >> >> Once you add the .machine directive to your inline asm though, you lose >> *all* such static checking for the instruction. So it's really not a >> panacea and has its own downsides. >=20 > Again, there should be a minimum number of those .machine directives > in inline asm as well, which tends to work out fine as long as the > entire kernel is built with the correct -march=3D option for the minimum > supported CPU, and stays away from inline asm that requires a higher > CPU level. There's really no advantage to them, and they're ugly and annoying and if we applied the concept consistently for all asm they would grow=20 to a very large number. The idea they'll give you good static checking just doesn't really pan out. Thanks, Nick