From: Manivannan Sadhasivam <mani@kernel.org>
To: lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org,
bhelgaas@google.com, helgaas@kernel.org, kishon@kernel.org,
vigneshr@ti.com, Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: stable@vger.kernel.org, linux-pci@vger.kernel.org,
linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH v4] PCI: j721e: Fix programming sequence of "strap" settings
Date: Mon, 08 Sep 2025 17:53:21 +0530 [thread overview]
Message-ID: <175733420164.9759.8251040864412190074.b4-ty@kernel.org> (raw)
In-Reply-To: <20250908120828.1471776-1-s-vadapalli@ti.com>
On Mon, 08 Sep 2025 17:38:27 +0530, Siddharth Vadapalli wrote:
> The Cadence PCIe Controller integrated in the TI K3 SoCs supports both
> Root-Complex and Endpoint modes of operation. The Glue Layer allows
> "strapping" the Mode of operation of the Controller, the Link Speed
> and the Link Width. This is enabled by programming the "PCIEn_CTRL"
> register (n corresponds to the PCIe instance) within the CTRL_MMR
> memory-mapped register space. The "reset-values" of the registers are
> also different depending on the mode of operation.
>
> [...]
Applied, thanks!
[1/1] PCI: j721e: Fix programming sequence of "strap" settings
commit: f842d3313ba179d4005096357289c7ad09cec575
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2025-09-08 12:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 12:08 [PATCH v4] PCI: j721e: Fix programming sequence of "strap" settings Siddharth Vadapalli
2025-09-08 12:23 ` Manivannan Sadhasivam [this message]
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