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From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>,
	Viken Dadhaniya <quic_vdadhani@quicinc.com>,
	Shazad Hussain <quic_shazhuss@quicinc.com>,
	Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH v1] arm64: dts: qcom: lemans: Correct QUP interrupt numbers
Date: Wed, 25 Mar 2026 22:19:29 -0500
Message-ID: <177449516592.60308.9671178778300798173.b4-ty@kernel.org>
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On Wed, 25 Mar 2026 18:30:37 +0530, Viken Dadhaniya wrote:
> Fix GIC_SPI interrupt numbers for QUPv3 SE6 nodes on Lemans SoC.
> Using incorrect interrupt lines can prevent IRQs from triggering
> and break I2C, SPI, and UART operation.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: lemans: Correct QUP interrupt numbers
      commit: a8c84db62c97dad3625c08d7aef4311a71fb0d27

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>