From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org, stable@vger.kernel.org
Subject: Re: [PATCH 1/5] drm/i915/dsi: Don't do DSC horizontal timing adjustments in command mode
Date: Thu, 26 Mar 2026 17:20:31 +0200 [thread overview]
Message-ID: <18c2a71298928c8a3ee39603d1a783a13c9e62b0@intel.com> (raw)
In-Reply-To: <20260326111814.9800-2-ville.syrjala@linux.intel.com>
On Thu, 26 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop adjusting the horizontal timing values based on the
> compression ratio in command mode. Bspec seems to be telling
> us to do this only in video mode, and this is also how the
> Windows driver does things.
>
> This should also fix a div-by-zero on some machines because due to
> the adjusted htotal ends up being so small that we end up with
> line_time_us==0 when trying to determine the vtotal value in
> command mode.
>
> Note that this doesn't actually make the display on the
> Huawei Matebook E work, but at least the kernel no longer
> explodes when the driver loads.
>
> Cc: stable@vger.kernel.org
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12045
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 53693f02d80e ("drm/i915/dsi: account for DSC in horizontal timings")
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c04327979678..a763f2b13ff2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -888,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> * non-compressed link speeds, and simplifies down to the ratio between
> * compressed and non-compressed bpp.
> */
> - if (crtc_state->dsc.compression_enable) {
> + if (is_vid_mode(intel_dsi) && crtc_state->dsc.compression_enable) {
> mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
> div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> }
> @@ -1502,7 +1502,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
>
> - if (pipe_config->dsc.compressed_bpp_x16) {
> + if (is_vid_mode(intel_dsi) && pipe_config->dsc.compressed_bpp_x16) {
> int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
> int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
--
Jani Nikula, Intel
prev parent reply other threads:[~2026-03-26 15:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260326111814.9800-1-ville.syrjala@linux.intel.com>
2026-03-26 11:18 ` [PATCH 1/5] drm/i915/dsi: Don't do DSC horizontal timing adjustments in command mode Ville Syrjala
2026-03-26 15:20 ` Jani Nikula [this message]
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