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b=2Jfmxol9wWJUIqtE23eq2N04AczQZtIRSiP/kHFUlzNh2L6V/DEZmWSsSKym4rNbhwFHox4pbMl1DLmid/KziDYpKqemXKf8YmzBQ17qMRODD0ZcYTm4l6G/tD/ytH5wm1VbX3Q5ksOnYh4w4sqTu9d4Q7nDtesdpqx3XX0PAW0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DM4PR12MB8476.namprd12.prod.outlook.com (2603:10b6:8:17e::15) by SJ5PPF183341E5B.namprd12.prod.outlook.com (2603:10b6:a0f:fc02::98c) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.10; Thu, 20 Nov 2025 18:35:44 +0000 Received: from DM4PR12MB8476.namprd12.prod.outlook.com ([fe80::2d79:122f:c62b:1cd8]) by DM4PR12MB8476.namprd12.prod.outlook.com ([fe80::2d79:122f:c62b:1cd8%6]) with mapi id 15.20.9343.009; Thu, 20 Nov 2025 18:35:43 +0000 Message-ID: <1a10e80d-23a6-4b35-bced-7b55cc6a5966@amd.com> Date: Thu, 20 Nov 2025 11:35:40 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 23/26] drm/amd/display: Correct DSC padding accounting To: Mario Limonciello , amd-gfx@lists.freedesktop.org Cc: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , Fangzhi Zuo , Dan Wheeler , Ray Wu , Ivan Lipski , Relja Vojvodic , Alex Deucher , stable@vger.kernel.org, Chris Park , Wenjing Liu References: <20251120181527.317107-1-alex.hung@amd.com> <20251120181527.317107-24-alex.hung@amd.com> <49c24aad-90cb-4d87-afe2-1a65d2d85e80@amd.com> Content-Language: en-US From: Alex Hung In-Reply-To: <49c24aad-90cb-4d87-afe2-1a65d2d85e80@amd.com> Content-Type: text/plain; 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I think the stable tag should be dropped on > this patch. Thanks. I will remove the Cc stable. > >> - This caused compliance failures or corruption >> >> [HOW] >> - Add padding to DSC pic width when required by HW, and do not re-add >>    when calculating reg values >> - Do not add padding when computing PPS values, and instead track padding >>    separately to add when calculating slice width values >> >> Cc: Mario Limonciello >> Cc: Alex Deucher >> Cc: stable@vger.kernel.org >> Reviewed-by: Chris Park >> Reviewed-by: Wenjing Liu >> Signed-off-by: Relja Vojvodic >> Signed-off-by: Alex Hung >> --- >>   drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c   | 2 +- >>   drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c     | 2 +- >>   drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c     | 2 +- >>   drivers/gpu/drm/amd/display/dc/link/link_dpms.c             | 3 ++- >>   .../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c  | 6 +++--- >>   5 files changed, 8 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c >> b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c >> index 4ee6ed610de0..3e239124c17d 100644 >> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c >> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c >> @@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx >> *pipe_ctx, bool enable) >>           dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >>           ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); >>           dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; >> -        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >> +        dsc_cfg.dsc_padding = 0; >>           dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); >>           dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); >> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c >> b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c >> index bf19ba65d09a..b213a2ac827a 100644 >> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c >> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c >> @@ -1061,7 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx >> *pipe_ctx, bool enable) >>           dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >>           ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); >>           dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; >> -        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >> +        dsc_cfg.dsc_padding = 0; >>           if (should_use_dto_dscclk) >>               dccg->funcs->set_dto_dscclk(dccg, dsc->inst, >> dsc_cfg.dc_dsc_cfg.num_slices_h); >> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c >> b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c >> index 7aa0f452e8f7..cb2dfd34b5e2 100644 >> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c >> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c >> @@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx >> *pipe_ctx, bool enable) >>           dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >>           ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); >>           dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; >> -        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >> +        dsc_cfg.dsc_padding = 0; >>           dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); >>           dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); >> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/ >> drivers/gpu/drm/amd/display/dc/link/link_dpms.c >> index 1b1ce3839922..77e049917c4d 100644 >> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c >> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c >> @@ -841,7 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx >> *pipe_ctx, bool enable) >>           dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >>           ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); >>           dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; >> -        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >> +        dsc_cfg.dsc_padding = 0; >>           if (should_use_dto_dscclk) >>               dccg->funcs->set_dto_dscclk(dccg, dsc->inst, >> dsc_cfg.dc_dsc_cfg.num_slices_h); >> @@ -857,6 +857,7 @@ void link_set_dsc_on_stream(struct pipe_ctx >> *pipe_ctx, bool enable) >>           } >>           dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; >>           dsc_cfg.pic_width *= opp_cnt; >> +        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >>           optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? >> OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; >> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/ >> dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/ >> dcn20_resource.c >> index 6679c1a14f2f..8d10aac9c510 100644 >> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c >> +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c >> @@ -1660,8 +1660,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct >> dc_state *new_ctx) >>           if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream >> || !stream->timing.flags.DSC) >>               continue; >> -        dsc_cfg.pic_width = (stream->timing.h_addressable + stream- >> >timing.h_border_left >> -                + stream->timing.h_border_right) / opp_cnt; >> +        dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding >> +                + stream->timing.h_border_left + stream- >> >timing.h_border_right) / opp_cnt; >>           dsc_cfg.pic_height = stream->timing.v_addressable + stream- >> >timing.v_border_top >>                   + stream->timing.v_border_bottom; >>           dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; >> @@ -1669,7 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct >> dc_state *new_ctx) >>           dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; >>           dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; >>           dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; >> -        dsc_cfg.dsc_padding = pipe_ctx- >> >dsc_padding_params.dsc_hactive_padding; >> +        dsc_cfg.dsc_padding = 0; >>           if (!pipe_ctx->stream_res.dsc->funcs- >> >dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) >>               return false; >