From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86BB2C10F1B for ; Tue, 13 Dec 2022 05:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234496AbiLMFJB (ORCPT ); Tue, 13 Dec 2022 00:09:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234623AbiLMFIf (ORCPT ); Tue, 13 Dec 2022 00:08:35 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5398F2037A; Mon, 12 Dec 2022 21:06:31 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BCNRlBL003799; Tue, 13 Dec 2022 05:06:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=ZqKCaBAFByLRQwrGF3Qm+jTzymSSI7/HMVAI+7LN6N8=; b=WEQhNHF+sOormm2yA1uP1vpJu3rhbK8IzhmeqXjlUIFm+V0nkD/MYPwgjwRwI2FTNv4F TtkMmv5pA9U1l6o/IQQmAZy8t5oIMEeP1i6lgoo6QMp2dqqWFk0Bw+Iwrd/Zy52owTo8 OBhSwK02uSHLNmM4+qhvmEQ/WDsm+b1JxBGpTvMrUPHdzy0nWBAHHko9XyjZxqbWoPYW CW8L81+/OnNbxo0mA8+EwhOyLvcf+jAvnwrCvGTi9nmQcdO3M0s/E3m3bSr10ldtzI9T GZ8+aDl4zDrWXFZ8nsRlodMwKf132+W7M5RIhKBfBZ5cZM9z+fweJbisOoRUAq3CHYMb RA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3medyp8txf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 05:06:22 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BD56Lh1015120 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 13 Dec 2022 05:06:21 GMT Received: from [10.50.38.23] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 21:06:16 -0800 Message-ID: <1ad4d35e-ad82-eb2f-5aea-882fcae2cac5@quicinc.com> Date: Tue, 13 Dec 2022 10:36:13 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v2 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks To: Manivannan Sadhasivam , , , , , CC: , , , , , , , , , References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> <20221212123311.146261-6-manivannan.sadhasivam@linaro.org> From: Sai Prakash Ranjan In-Reply-To: <20221212123311.146261-6-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: le0mcLfIjkDUMgHTO8w9kd-V7WofPUw9 X-Proofpoint-GUID: le0mcLfIjkDUMgHTO8w9kd-V7WofPUw9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-13_02,2022-12-12_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 bulkscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212130046 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 12/12/2022 6:03 PM, Manivannan Sadhasivam wrote: > The LLCC block has several banks each with a different base address > and holes in between. So it is not a correct approach to cover these > banks with a single offset/size. Instead, the individual bank's base > address needs to be specified in devicetree with the exact size. > > While at it, let's also fix the size of the llcc_broadcast_base to cover > the whole region. > > Also, let's get rid of reg-names property as it is not needed anymore. > The driver is expected to parse the reg field based on index to get the > addresses of each LLCC banks. > > Cc: # 5.13 > Fixes: 0392968dbe09 ("arm64: dts: qcom: sc7280: Add device tree node for LLCC") > Reported-by: Parikshit Pareek > Signed-off-by: Manivannan Sadhasivam > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 0adf13399e64..90e11cbbaf88 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3579,8 +3579,8 @@ gem_noc: interconnect@9100000 { > > system-cache-controller@9200000 { > compatible = "qcom,sc7280-llcc"; > - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; > - reg-names = "llcc_base", "llcc_broadcast_base"; > + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, > + <0 0x09600000 0 0x58000>; > interrupts = ; > }; > Reviewed-by: Sai Prakash Ranjan