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Tue, 13 May 2025 00:47:41 -0700 (PDT) From: Jerome Brunet To: Da Xue Cc: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , stable@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] clk: meson-g12a: add missing fclk_div2 to spicc In-Reply-To: <20250512142617.2175291-1-da@libre.computer> (Da Xue's message of "Mon, 12 May 2025 10:26:16 -0400") References: <20250512142617.2175291-1-da@libre.computer> User-Agent: mu4e 1.12.9; emacs 30.1 Date: Tue, 13 May 2025 09:47:40 +0200 Message-ID: <1jecwtymsj.fsf@starbuckisacylon.baylibre.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon 12 May 2025 at 10:26, Da Xue wrote: > SPICC is missing fclk_div2 which causes the spicc module to output sclk at > 2.5x the expected rate. Adding the missing fclk_div2 resolves this. I had to re-read that a few times to get the what the actual problem is. If you don't mind, I'll amend the commit message with ''' SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes are wrong on this clock. This causes the spicc module to output sclk at 2.5x the expected rate when clock index 3 is picked. Adding the missing fclk_div2 resolves this. ''' Is that OK with you Da ? > > Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks") > Cc: # 6.1 > Signed-off-by: Da Xue > --- > Changelog: > > v2 -> v3: remove gp0 > v1 -> v2: add Fixes as an older version of the patch was sent as v1 > --- > drivers/clk/meson/g12a.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > index 4f92b83965d5a..b72eebd0fa474 100644 > --- a/drivers/clk/meson/g12a.c > +++ b/drivers/clk/meson/g12a.c > @@ -4099,6 +4099,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { > { .hw = &g12a_clk81.hw }, > { .hw = &g12a_fclk_div4.hw }, > { .hw = &g12a_fclk_div3.hw }, > + { .hw = &g12a_fclk_div2.hw }, > { .hw = &g12a_fclk_div5.hw }, > { .hw = &g12a_fclk_div7.hw }, > }; -- Jerome