From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-Id: <20130911042854.607451582@goodmis.org> Date: Wed, 11 Sep 2013 00:27:22 -0400 From: Steven Rostedt To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Oskar Schirmer , Fabio Estevam , Mark Brown Subject: [015/251] ASoC: sglt5000: Fix SGTL5000_PLL_FRAC_DIV_MASK References: <20130911042707.738353451@goodmis.org> Content-Disposition: inline; filename=0015-ASoC-sglt5000-Fix-SGTL5000_PLL_FRAC_DIV_MASK.patch Sender: linux-kernel-owner@vger.kernel.org List-ID: 3.6.11.9-rc1 stable review patch. If anyone has any objections, please let me know. ------------------ From: Fabio Estevam [ Upstream commit 5c78dfe87ea04b501ee000a7f03b9432ac9d008c ] SGTL5000_PLL_FRAC_DIV_MASK is used to mask bits 0-10 (11 bits in total) of register CHIP_PLL_CTRL, so fix the mask to accomodate all this bit range. Reported-by: Oskar Schirmer Signed-off-by: Fabio Estevam Signed-off-by: Mark Brown Cc: stable@vger.kernel.org Signed-off-by: Steven Rostedt --- sound/soc/codecs/sgtl5000.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h index 8a9f435..d3a68bb 100644 --- a/sound/soc/codecs/sgtl5000.h +++ b/sound/soc/codecs/sgtl5000.h @@ -347,7 +347,7 @@ #define SGTL5000_PLL_INT_DIV_MASK 0xf800 #define SGTL5000_PLL_INT_DIV_SHIFT 11 #define SGTL5000_PLL_INT_DIV_WIDTH 5 -#define SGTL5000_PLL_FRAC_DIV_MASK 0x0700 +#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff #define SGTL5000_PLL_FRAC_DIV_SHIFT 0 #define SGTL5000_PLL_FRAC_DIV_WIDTH 11 -- 1.7.10.4