From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Paul Stewart , Rajkumar Manoharan , "John W. Linville" , Ben Hutchings , Jianguo Wu Subject: [PATCH 3.4 045/134] ath9k_hw: Enable hw PLL power save for AR9462 Date: Wed, 9 Apr 2014 20:22:41 -0700 Message-Id: <20140410032305.854366586@linuxfoundation.org> In-Reply-To: <20140410032259.587501440@linuxfoundation.org> References: <20140410032259.587501440@linuxfoundation.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: 3.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Rajkumar Manoharan commit 1680260226a8fd2aab590319da83ad8e610da9bd upstream. This reduced the power consumption to half in full and network sleep. Cc: Paul Stewart Signed-off-by: Rajkumar Manoharan Signed-off-by: John W. Linville [bwh: Backported to 3.2: - INIT_INI_ARRAY macro requires an explicit size argument - Remove the now-redundant macro PCIE_PLL_ON_CREQ_DIS_L1_2P0] Signed-off-by: Ben Hutchings Cc: Jianguo Wu Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/ath/ath9k/ar9003_hw.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -33,9 +33,6 @@ */ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) { -#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ - ar9462_pciephy_pll_on_clkreq_disable_L1_2p0 - #define AR9462_BB_CTX_COEFJ(x) \ ar9462_##x##_baseband_core_txfir_coeff_japan_2484 @@ -312,13 +309,13 @@ static void ar9003_hw_init_mode_regs(str /* Awake -> Sleep Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdes, - PCIE_PLL_ON_CREQ_DIS_L1_2P0, - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), + ar9462_pciephy_clkreq_disable_L1_2p0, + ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0), 2); /* Sleep -> Awake Setting */ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, - PCIE_PLL_ON_CREQ_DIS_L1_2P0, - ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), + ar9462_pciephy_clkreq_disable_L1_2p0, + ARRAY_SIZE(ar9462_pciephy_clkreq_disable_L1_2p0), 2); /* Fast clock modal settings */