From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-Id: <20140619215140.259138132@linutronix.de> Date: Thu, 19 Jun 2014 21:52:23 -0000 From: Thomas Gleixner To: LKML Cc: Viresh Kumar , Mike Turquette , spear-devel@list.st.com, stable@vger.kernel.org Subject: [patch 1/2] clk: spear3xx: Use proper control register offset References: <20140619214858.755664030@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Disposition: inline; filename=spear-clk-fix-crap.patch Sender: linux-kernel-owner@vger.kernel.org List-ID: The control register is at offset 0x10, not 0x0. This is wreckaged since commit 5df33a62c (SPEAr: Switch to common clock framework). Signed-off-by: Thomas Gleixner Cc: stable@vger.kernel.org --- drivers/clk/spear/spear3xx_clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: linux/drivers/clk/spear/spear3xx_clock.c =================================================================== --- linux.orig/drivers/clk/spear/spear3xx_clock.c +++ linux/drivers/clk/spear/spear3xx_clock.c @@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi /* array of all spear 320 clock lookups */ #ifdef CONFIG_MACH_SPEAR320 -#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) +#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) #define SPEAR320_UARTX_PCLK_MASK 0x1