From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 23 Apr 2015 13:32:36 -0700 From: Andi Kleen To: Thomas Gleixner Cc: Alexander Shishkin , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Don Zickus , Frederic Weisbecker , Adrian Hunter , Anton Blanchard , Michael Ellerman , linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v1] watchdog: Use a reference cycle counter to avoid scaling issues Message-ID: <20150423203236.GJ13605@tassilo.jf.intel.com> References: <1429801408-11309-1-git-send-email-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-ID: On Thu, Apr 23, 2015 at 10:01:04PM +0200, Thomas Gleixner wrote: > On Thu, 23 Apr 2015, Alexander Shishkin wrote: > > > The problem with using cycle counter for NMI watchdog is that its > > frequency changes with the corresponding core's frequency. This means > > that, in particular, if the core frequency scales up, watchdog NMI will > > arrive more frequently than what user requested through watchdog_thresh > > and also increasing the probability of setting off the hardlockup detector, > > because the corresponding hrtimer will keep firing at the same intervals > > regardless of the core frequency. And, if the core can turbo to up to 2.5x > > its base frequency (and therefore TSC) [1], we'll have the hrtimer and NMI > > So you are saying that this M-5Y10 has a non-constant TSC again? You > really can't be serious about that. The TSC is constant, but the maximum frequency can be >=2.5TSC, so the watchdog which uses cycles can have that much error. -Andi -- ak@linux.intel.com -- Speaking for myself only