From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.codeaurora.org ([198.145.29.96]:46631 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932820AbbHZSgh (ORCPT ); Wed, 26 Aug 2015 14:36:37 -0400 Date: Wed, 26 Aug 2015 11:36:35 -0700 From: Stephen Boyd To: Govindraj Raja Cc: linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Michael Turquette , Zdenko Pulitika , Kevin Cernekee , Ralf Baechle , Andrew Bresticker , James Hartley , Damien Horsley , James Hogan , Ezequiel Garcia , Sergei Shtylyov , stable@vger.kernel.org Subject: Re: [PATCH v6 2/4] clk: pistachio: Fix override of clk-pll settings from boot loader Message-ID: <20150826183635.GP19120@codeaurora.org> References: <1440605500-13274-1-git-send-email-Govindraj.Raja@imgtec.com> <1440605500-13274-3-git-send-email-Govindraj.Raja@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1440605500-13274-3-git-send-email-Govindraj.Raja@imgtec.com> Sender: stable-owner@vger.kernel.org List-ID: On 08/26, Govindraj Raja wrote: > From: Zdenko Pulitika > > PLL enable callbacks are overriding PLL mode (int/frac) and > Noise reduction (on/off) settings set by the boot loader which > results in the incorrect clock rate. > > PLL mode and noise reduction are defined by the DSMPD and DACPD bits > of the PLL control register. PLL .enable() callbacks enable PLL > by deasserting all power-down bits of the PLL control register, > including DSMPD and DACPD bits, which is not necessary since > these bits don't actually enable/disable PLL. > > This commit fixes the problem by removing DSMPD and DACPD bits > from the "PLL enable" mask. > > Fixes: 43049b0c83f17("CLK: Pistachio: Add PLL driver") > Cc: # 4.1 > Reviewed-by: Andrew Bresitcker > Signed-off-by: Zdenko Pulitika > Signed-off-by: Govindraj Raja > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project